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BQ25708 Folha de dados(PDF) 19 Page - Texas Instruments |
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BQ25708 Folha de dados(HTML) 19 Page - Texas Instruments |
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19 / 94 page ![]() 8.6 Timing Requirements (continued) MIN NOM MAX UNIT t(BUF) Bus free time between START and STOP condition 1.3 µs FS(CL) Clock Frequency 10 400 kHz HOST COMMUNICATION FAILURE ttimeout I2C bus release timeout(1) 25 35 ms tDeg_WD Deglitch for watchdog reset signal 10 ms tWDI Watchdog timeout period, ChargeOption() bit [14:13] = 01(2) 4 5.5 7 s Watchdog timeout period, ChargeOption() bit bit [14:13] = 10(2) 70 88 105 s Watchdog timeout period, ChargeOption() bit bit [14:13] = 11(2) 140 175 210 s (1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms). (2) User can adjust threshold via I2C ChargeOption() REG0x01/00(). www.ti.com BQ25713, BQ25713B SLUSD83C – JUNE 2018 – REVISED MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: BQ25713 BQ25713B |
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