BQ25708 datasheet(33/94 Pages) TI2

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SDA

SCL

Data line stable;

Data valid

Change

of data

allowed

Figure 9-4. Bit Transfer on the I2C Bus

9.5.1.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START

condition, and free after the STOP condition.

START (S)

STOP (P)

SDA

SCL

SDA

SCL

Figure 9-5. START and STOP Conditions

9.5.1.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant

Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some

other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data

transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

SCL

SDA

START or

Repeated

START

S or Sr

MSB

ACK

Acknowledgement

signal from slave

ACK

Acknowledgement

signal from receiver

STOP or

Repeated

START

P or Sr

Figure 9-6. Data Transfer on the I2C Bus

9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge 9th clock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line

LOW and it remains stable LOW during the HIGH period of this clock pulse.

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BQ25713, BQ25713B

SLUSD83C – JUNE 2018 – REVISED MAY 2023

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