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BQ25708 Folha de dados(PDF) 75 Page - Texas Instruments

Nome de Peças BQ25708
Descrição Electrónicos  BQ25713, BQ25713B I2C Narrow VDC Buck-Boost Battery Charge Controller With System Power Monitor and Processor Hot Monitor
PDF  94 Pages
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Fabricante Electrônico  TI2 [Texas Instruments]
Página de início  https://www.ti.com
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IRIPPLE_BOOST = (VIN × DBOOST) / (fS × L)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9 V to 12.6 V for 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives
the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12 V to
16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20 – 40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
10.2.2.3 Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current (plus system current there is any system load) when duty cycle
is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS
current occurs where the duty cycle is closest to 50% and can be estimated by Equation 5:
CIN
CHG
I
= I
D × (1
D)
´
-
(5)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed in front of RAC current sensing and as close as possible to the power stage half bridge MOSFETs.
Capacitance after RAC before power stage half bridge should be limited to 10 nF + 1 nF referring to Figure 10-2.
Because too large capacitance after RAC could filter out RAC current sensing ripple information. Voltage rating of
the capacitor must be higher than normal input voltage level, 25-V rating or higher capacitor is preferred for 19-V
to 20-V input voltage. The minimum input effective capacitance recommendation is shown in Table 10-1.
Ceramic capacitors (MLCC) show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias
voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead
to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the
manufacturer's datasheet about the derating performance with a dc bias voltage applied. It may be necessary to
choose a higher voltage rating or nominal capacitance value in order to get the required effective capacitance
value at the operating point. Considering the 25 V 0603 package MLCC capacitance derating under 19-V to 20-V
input voltage, the recommended practical capacitors configuration can also be found in Table 10-1. Tantalum
capacitors (POSCAP) can avoid dc-bias effect and temperature variation effect which is recommended for 90 W
to 130 W higher power application.
Table 10-1. Minimum Input Capacitance Requirement
INPUT CAPACITORS VS TOTAL INPUT
POWER
65W
90W
130W
Minimum effective input capacitance
4 μF
6 μF
13 μF
Minimum practical input capacitors
configuration
4*10 μF (0603 25 V MLCC)
6*10 μF (0603 25 V MLCC)
3*10 μF (0603 25 V MLCC)
1* 10 μF (25 V to 35 V
POSCAP)
10.2.2.4 Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. To
get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed
between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25-V X7R or X5R for output capacitor. Minimum
7 pcs of 10-μF 0603 package capacitor is suggested to be placed as close as possible to Q3&Q4 half bridge
(between Q4 drain and Q3 source terminal). Total minimum output effective capacitance along VSYS distribution
line is 50 μF refers to Table 10-2. Recommend to place minimum 20-μF MLCC capacitors after the charge
current sense resistor for best stability.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias
voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead
to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the
manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary
www.ti.com
BQ25713, BQ25713B
SLUSD83C – JUNE 2018 – REVISED MAY 2023
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: BQ25713 BQ25713B



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