BQ25708 datasheet(7/94 Pages) TI2

7 / 94 page

Table 7-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

CHRG_OK

Open drain active high indicator to inform the system good power source is connected to the

charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5V or

falls below 24.5V, CHRG_OK is HIGH after 50ms deglitch time. When VBUS falls below 3.2

V or rises above 26 V, CHRG_OK is LOW. When any fault occurs, CHRG_OK is asserted

LOW.

CMPIN

Input of independent comparator. The independent comparator compares the voltage

sensed on CMPIN pin with internal reference, and its output is on CMPOUT pin. Internal

reference, output polarity and deglitch time is selectable by the I2C host. With polarity HIGH

(REG0x30[6] = 1), place a resistor between CMPIN and CMPOUT to program hysteresis.

With polarity LOW (REG0x30[6] = 0), the internal hysteresis is 100 mV. If the independent

comparator is not in use, tie CMPIN to ground.

CMPOUT

Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup

supply rail. Internal reference, output polarity and deglitch time are selectable by the I2C

host.

COMP2

Buck boost converter compensation pin 2. Refer to BQ2571X EVM schematic for COMP2

pin RC network.

COMP1

Buck boost converter compensation pin 1. Refer to BQ2571X EVM schematic for COMP1

pin RC network.

OTG/VAP

Active HIGH to enable OTG or VAP modes. When REG0x34[5]=1, pulling high OTG/VAP

pin and setting REG0x35[4]=1 can enable OTG mode. When REG0x34[5]=0, pulling high

OTG/VAP pin is to enable VAP mode.

HIDRV1

Buck mode high side power MOSFET (Q1) driver. Connect to high side n-channel MOSFET

gate.

HIDRV2

Boost mode high side power MOSFET(Q4) driver. Connect to high side n-channel MOSFET

gate.

IADPT

The adapter current monitoring output pin. V(IADPT) = 20 or 40 × (V(ACP) – V(ACN)) with ratio

selectable in REG0x00[4]. Place a resistor from the IADPT pin to ground corresponding to

the inductance in use. For a 2.2 µH inductance, the resistor is 137 kΩ. Place a 100-pF

or less ceramic decoupling capacitor from IADPT pin to ground. IADPT output voltage is

clamped below 3.3 V.

IBAT

The battery current monitoring output pin. V(IBAT) = 8 or 16 × (V(SRP) – V(SRN)) for charge

current, or V(IBAT) = 8 or 16 × (V(SRN) – V(SRP)) for discharge current, with ratio selectable in

REG0x00[3]. Place a 100-pF or less ceramic decoupling capacitor from IBAT pin to ground.

This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.

ILIM_HIZ

Input current limit setting pin. Program ILIM_HIZ voltage by connecting a resistor divider

from supply rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V

+ 40 × IDPM × RAC, in which IDPM is the target input current. The input current limit used

by the charger is the lower setting of ILIM_HIZ pin and REG0x0F/0E(). When the pin voltage

is below 0.4 V, the device enters Hi-Z mode with low quiescent current. When the pin voltage

is above 0.8 V, the device is out of Hi-Z mode.

LODRV1

Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET

gate.

LODRV2

Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET

gate.

PGND

GND

Device power ground.

PROCHOT

Active low open drain output of processor hot indicator. It monitors adapter input current,

battery discharge current, and system voltage. After any event in the PROCHOT profile is

triggered, a pulse is asserted. The minimum pulse width is adjustable in REG0x23[6:3].

PSYS

Current mode system power monitor. The output current is proportional to the total power

from the adapter and the battery. The gain is selectable through I2C. Place a resistor from

PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output

voltage is clamped below 3.3 V. Place a capacitor in parallel with the resistor for filtering.

REGN

PWR

6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS

above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power

ground. REGN pin output is for power stage gate drive.

SCL

I2C clock input. Connect to clock line from the host controller or smart battery. Connect a

10-kΩ pullup resistor according to I2C specifications.

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BQ25713, BQ25713B

SLUSD83C – JUNE 2018 – REVISED MAY 2023

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