CC1010-RTY1 datasheet(80/152 Pages) TI

80 / 152 page

CC1010

SWRS047

Page 80 of 152

to 250 kHz, then the conversion time is 44

µs.

single-conversion

mode

each

conversion is initiated by setting the

ADCON.ADCRUN control bit. The ADC

interrupt

flags

EXIF.ADIF

and

ADCON2.ADCIF are set by hardware if the

8 MSB of the latest sampled value is

greater than or equal to the threshold

value stored in the ADTRH register. An

interrupt service routine is then executed if

the interrupt enable flags EIE.ADIE and

ADCON2.ADCIE are set. To always get an

interrupt upon completion of a conversion,

ADTRH

should

set

The

ADCON.ADCRUN control bit is cleared by

hardware when the conversion is finished.

In the multi-conversion modes the ADC

starts a new conversion every 11th ADC

clock cycle. All multi-conversion modes

can

stopped

clearing

ADCON.ADCRUN, after which the ADC will

abort its current conversion and then stop.

In all modes an action is taken when the 8

MSB of the latest sample value is greater

than or equal to the value written in

ADTRH; these are:

Multi-conversion, continuous. When the

threshold comparison holds true (value

≥

ADTRH⋅ 4) an interrupt is generated and

the corresponding interrupt service routine

is then executed if the interrupt enable

flags EIE.ADIE and ADCON2.ADCIE are

set. The ADC will continue its conversions

regardless of the result of the threshold

comparison. To always get an interrupt

upon completion of a conversion, ADTRH

should be set to 0.

Multi-conversion, stopping. When the

threshold comparison holds true (value

≥

ADTRH⋅ 4) an interrupt is generated and

the corresponding interrupt service routine

is then executed if the interrupt enable

flags EIE.ADIE and ADCON2.ADCIE are

set. The ADC will stop when the threshold

comparison

holds

true,

clearing

ADCON.ADCRUN.

Multi-conversion,

reset-generating.

When the threshold comparison holds true

(value

≥ ADTRH⋅ 4) a system reset is

generated. This mode can be used in

conjunction with the 8051's stop mode and

the 32 kHz oscillator to achieve very low

power consumption while monitoring a

signal. The value stored in ADDATH and

ADDATL is not affected by a reset, so that

the sampled value can be read back after

the reset has taken effect.

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