CC1010-RTY1 datasheet(63/152 Pages) TI

63 / 152 page

CC1010

SWRS047

Page 63 of 152

16.5 Watchdog Timer

CC1010 includes an 8-bit watchdog timer

that is clocked by the system clock. The

clock is divided by a number in the range

from 2048 to 16384, controllable through

WDT.WDTPRE(1:0). The divided clock

controls an 8-bit timer, which generates

system reset upon overflow. A block

diagram for the Watchdog Timer is shown

in Figure 14.

Chipcon recommends that the watchdog

timer should be disabled when the

CC1010

is clocked from the 32 kHz oscillator

(Clock mode 1).

Note that the watchdog timer is not active

in Power-down mode, and therefore

cannot wake up the

CC1010 from Power-

Down mode.

WDT (0xD2) - Watchdog Timer Control Register

Bit

Name

R/W

Reset value

Description

Reserved, read as 0

WDTSE

R/W

Watchdog Timer Stop Enable, used to disable the

watchdog timer

WDTEN

R/W

Watchdog Timer Enable / Disable

0 : The watchdog timer is disabled

1 : The watchdog timer is enabled

The watchdog timer is enabled after reset. To disable the

watchdog timer,

WDTSE must be used as described in this

section.

WDTCLR

R0/

Watchdog timer clear signal.

WDTCLR must periodically

be set to prevent the watchdog timer from resetting the

system.

WDTCLR is cleared by hardware, and is thus

always read 0.

0 : Normal watchdog operation

1 : Watchdog timer is cleared.

1:0

WDTPRE.1

R/W

Watchdog timer prescaler control.

WDTPRE(1:0)

controls the division of the main crystal oscillator clock to

generate the watchdog timer clock.

00 : fWDT = fXOSC / 2048

01 : fWDT = fXOSC / 4096

10 : fWDT = fXOSC / 8192

11 : fWDT = fXOSC / 16384

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