AD6654SLASHPCB datasheet(20/88 Pages) AD

20 / 88 page

AD6654

Rev. 0 | Page 20 of 88

Name

Type

Pin Number

Function

DDC INPUTS

CLK

Input

A11

DDC Clock Input.

SYNC0

Input

T10

Synchronization Input 0. SYNC pins are independent of channels.

SYNC1

Input

R11

Synchronization Input 1.

SYNC2

Input

P11

Synchronization Input 2.

SYNC3

Input

T11

Synchronization Input 3.

DDC OUTPUTS

EXPC [2:0]

Output

D11, C11, B11

External VGA Gain Control Bits. GND all pins if not used.

DDC OUTPUT PORTS

PCLK

Bi-dir

Parallel Output Port Clock. PCLK is bi-directional: master mode = output, slave mode = input.

PADATA[15:0]

Output

See

Table 12

Parallel Output Port A Data Bus.

PACH[2:0]

Output

D8, R5, C8

Channel Indicator Output Port A.

PAIQ

Output

Parallel Port A I/Q Data Indicator. Logic 1 indicates I data on data bus.

PAGAIN

Output

Parallel Port A Gain Word Output Indicator. Logic 1 indicates gain word on data bus.

PAACK

Input

Parallel Port A Acknowledge (Active High).

PAREQ

Output

Parallel Port A Request (Active High).

PBDATA[15:0]

Output

See

Table 12

Parallel Output Port B Data Bus.

PBCH[2:0]

Output

P10, P8, R8

Channel Indicator Output Port B.

PBIQ

Output

Parallel Port B I/Q Data Indicator. Logic 1 indicates I data on data bus.

PBGAIN

Output

R10

Parallel Port B Gain Word Output Indicator. Logic 1 indicates gain word on data bus.

PBACK

Input

Parallel Port B Acknowledge (Active High).

PBREQ

Output

Parallel Port B Request (Active High)

PCDATA[15:0]

Output

See

Table 12

Parallel Output Port C Data Bus.

PCCH[2:0]

Output

M5, A6, R1

Channel Indicator Output Port C.

PCIQ

Output

Parallel Port C I/Q Data Indicator. Logic 1 indicates I data on data bus.

PCGAIN

Output

Parallel Port C Gain word Output Indicator. Logic 1 indicates gain word on data bus.

PCACK

Input

Parallel Port C Acknowledge (Active High).

PCREQ

Output

Parallel Port C Request (Active High).

MICROPORT CONTROL

D[15:0]

Bi-Dir

See

Table 12

Bidirectional Microport Data. This bus is three-stated when CS is high.

A[7:0]

Input

See

Table 12

Microport Address Bus.

DS (RD)

Input

Active Low Data Strobe, MODE = 1. Active low read strobe when MODE = 0.

DTACK (RDY)1

Output

Active Low Data Acknowledge, MODE = 1. Microport status pin when MODE = 0. Terminate

to VDDIO through external 1 kΩ pull-up resistor.

R/W (WR)

Input

Read/Write Strobe, MODE = 1. Active low write strobe when MODE = 0.

MODE

Input

Mode Select. Logic 0 = Intel® mode, Logic 1 = Motorola mode.

Input

Active Low Chip Select. Logic 1 three-states the microport data bus.

CPUCLK

Input

Microport CLK Input. (Input only.)

CHIPID[3:0]

Input

C1, E1, B3, B2

Chip ID Input Pins.

SERIAL PORT CONTROL

SCLK

Input

Serial Clock. Should have a rise/fall time of 3ns max.

SDO1

Output

Serial Port Data Output. Terminate to VDDIO through external 1 kΩ pull-up resistor.

SDI2

Input

Serial Port Data Input.

STFS

Input

Serial Transmit Frame Sync.

SRFS

Input

Serial Receive Frame Sync.

SCS

Input

Serial Chip Select.

MSB_FIRST

Input

Most Significant Bit_First. Selects MSB_FIRST into SDI pin, and MSB_FIRST out of SDO pin.

Logic 1 = MSB_FIRST; Logic 0 = LSB_FIRST

SMODE

Input

Serial Mode Select.

MISC PINS

DNC

-------

B12, T9

Do Not Connect.

IRP1

Output

Interrupt Pin (Active Low). Terminate to VDDIO through external 1 kΩ pull-up resistor.

RESET

Input

Master Reset, Active Low.

EXT_FILTER

Input

PLL Loop Filter (Analog Pin). Connect to VDDCORE through series 250 Ω and 0.01 µF

capacitor.

1 Pins with internal pull-up resistor of nominal 70 kΩ.

2 Pins with internal pull-down resistor of nominal 70 kΩ.

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