AD6654SLASHPCB datasheet(5/88 Pages) AD

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AD6654

Rev. 0 | Page 5 of 88

can perform. It can also allow complex filtering operations to be

achieved in the programmable filters.

The digital AGC provides the user with scaled digital outputs

based on the rms level of the signal present at the output of the

digital filters. The user can set the requested level and time

constant of the AGC loop for optimum performance of the

postprocessor. This is a critical function in the base station for

CDMA application, where the power level must be well

controlled going into the RAKE receivers. It has programmable

clipping and rounding control to provide different output

resolutions.

The overall filter response for the AD6654 is the composite of

all the combined filter stages. Each successive filter stage is

capable of narrower transition bandwidths, but requires a

greater number of CLK cycles to calculate the output. The

AD6654 features a fractional clock multiplier that uses the ADC

clock (which is slower than the DDC’s processing speed) to

produce a DDC master clock up to 200 MHz. This feature

allows fractional multiplication of the input clock to allow the

DDC to function at maximum speed while maintaining edge

identity to the ADC clock.

More decimation in the first filter stage minimizes overall

power consumption. Data from the device is interfaced to a

DSP/FPGA/baseband processor via high speed parallel ports

(preferred), or a DSP-compatible microprocessor interface.

The AD6654 is available in 4-channel and 6-channel versions.

The primary focus of the data sheet is on the 6-channel part.

The only difference between the 6-channel and 4-channel

devices is that, on the 4-channel version, Channel 4 and

Channel 5 are not available (see Figure 1). The 4-channel device

has the same DDC input port features, output ports, and

memory map as the 6-channel device. On the 4-channel

version, the memory map section for Channel 4 and Channel 5

can be programmed and read back, but the two extra channels

are disabled internally.

PRODUCT HIGHLIGHTS

Integrated 14-bit, 92.16 MSPS ADC.

Track-and-hold amplifier analog input for excellent IF

sampling up to 200 MHz.

Four or six independent digital filtering channels.

RMS/peak power monitoring of the ADC data port and

96 dB range AGCs before the output ports.

Three programmable RAM coefficient filters, three half-

band filters, two fixed coefficient filters, and one fifth-

order CIC filter per channel.

Complex filtering by combining filtering capability of

multiple channels.

Three 16-bit parallel output ports operating at up to

200 MHz clock.

Blackfin®- and TigerSHARC®-compatible, 8-/16-bit

microprocessor port.

Synchronous serial communications port is compatible

with most serial interface standards: SPORT, SPI, and SSR.

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