AD6654SLASHPCB datasheet(32/88 Pages) AD

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AD6654

Rev. 0 | Page 32 of 88

POWER MONITOR

HOLDING

ACCUMULATOR

MEMORY

MAP

FROM

MEMORY

MAP

FROM

INPUT

PORTS

LOAD

CLEAR

LOAD

IS COUNT = 1?

DOWN

COUNTER

INTERRUPT

CONTROLLER

POWER MONITOR

PERIOD REGISTER

Figure 45. ADC Input Mean Power Monitoring Block Diagram

THRESHOLD CROSSING MODE

Control Bits 10

In this mode of operation, the magnitude of the input port

signal is monitored over a programmable time period (given

by AMPR) to count the number of times it crosses a certain

programmable threshold value. This mode is set by program-

ming Logic 1x (where x is a don’t care bit) in the power monitor

function select bits in the power monitor control register of the

DDC input port. Before activating this mode, the user needs to

program the 24-bit AMPR and the 10-bit upper threshold register

of the DDC input port. The same upper threshold register is

used for both power monitoring and gain control (see the ADC

Gain Control section).

After entering this mode, the value in the AMPR is loaded into

a monitor period timer, and the countdown is started. The

magnitude of the input signal is compared to the upper

threshold register (programmed previously) on each input clock

cycle. If the input signal has a magnitude greater than the upper

threshold register, then the MSR register is incremented by 1.

The initial value of the MSR is set to 0. This comparison and

incrementing of the MSR register continues until the monitor

period timer reaches a count of 1.

When the monitor period timer reaches a count of 1, the value

in the MSR is transferred to the power monitor holding register,

which can be read through the microport or the serial port. The

monitor period timer is reloaded with the value in the AMPR,

and the countdown is started. The MSR register is also cleared

to a value of 0. If interrupts are enabled, an interrupt is gener-

ated, and the interrupt status register is updated when the

AMPR reaches a count of 1. Figure 46 illustrates the threshold

crossing logic. The value in the MSR is the number of samples

that have an amplitude greater than the threshold register.

POWER MONITOR

HOLDING

COMPARE

> B

UPPER

THRESHOLD

COMPARE

> B

MEMORY

MAP

FROM

MEMORY

MAP

FROM

MEMORY

MAP

FROM

INPUT

PORTS

LOAD

CLEAR

LOAD

IS COUNT = 1?

DOWN

COUNTER

INTERRUPT

CONTROLLER

POWER MONITOR

PERIOD REGISTER

Figure 46. ADC Input Threshold Crossing Block Diagram

ADDITIONAL CONTROL BITS

For additional flexibility in the power monitoring process, two

control bits are provided in the power monitor control register.

The two control bits are the disable monitor period timer bit

and the clear-on-read bit. These options have the same function

in all three modes of operation.

Disable Monitor Period Timer Bit

When the disable monitor period timer bit is written with

Logic 1, the timer continues to run but does not cause the

contents of the MSR to be transferred to the holding register

when the count reaches 1. This function of transferring the

MSR to the power monitor holding register and resetting the

MSR is now controlled by a read operation on the microport or

serial port.

When a microport or serial port read is performed on the

power monitor holding register, the MSR value is transferred to

the holding register. After the read operation, the timer is

reloaded with the AMPR value. If the timer reaches 1 before the

microport or serial port read, the MSR value is not transferred

to the holding register, as in normal operation. The timer still

generates an interrupt on the AD6654 interrupt pin and updates

the interrupt status register. An interrupt appears on the IRP

pin, if interrupts are enabled in the interrupt enable register.

Clear-on-Read Bit

This control bit is valid only when the disable monitor period

timer bit is Logic 1. When both of these bits are set, a read

operation to either the microport or the serial port reads the

MSR value, and the monitor period timer is reloaded with the

AMPR value. The MSR is cleared (written with current input

signal magnitude in peak power and mean power modes;

written with a 0 in threshold crossing mode), and normal

operation continues.

When the monitor period timer is disabled and the clear-on-

read bit is set, a read operation to the power monitor holding

monitor loop restarts.

If the clear-on-read bit is Logic 0, the read operation to the

microport or serial port does not clear the MSR value after it is

transferred into the holding register. The value from the

previous monitor time period persists, and it continues to be

compared, accumulated, or incremented, based on new input

signal magnitude values.

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