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AD6654/PCB Folha de dados(PDF) 11 Page - Analog Devices

Nome de Peças AD6654/PCB
Descrição Electrónicos  14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver
PDF  88 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD6654/PCB Folha de dados(HTML) 11 Page - Analog Devices

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AD6654
Rev. 0 | Page 11 of 88
SERIAL PORT TIMING CHARACTERISTICS
Table 9.
Parameter1, 2, 3
Temp
Test Level
Min
Typ
Max
Unit
SERIAL PORT CLOCK TIMING REQUIREMENTS
tSCLK
SCLK Period
Full
IV
10.0
ns
tSCLKL
SCLK Low Time
Full
IV
1.60
0.5 × tSCLK
ns
tSCLKH
SCLK High Time
Full
IV
1.60
0.5 × tSCLK
ns
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
tSSDI
SDI to
↑SCLK Setup Time
Full
IV
1.30
ns
tHSDI
SDI to
↑SCLK Hold Time
Full
IV
0.40
ns
tSSCS
SCS to
↑SCLK Setup Time
Full
IV
4.12
ns
tHSCS
SCS to
↑SCLK Hold Time
Full
IV
−2.78
ns
tDSDO
↑SCLK to SDO Delay Time
Full
IV
4.28
7.96
ns
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
tSSDI
SDI to
↑SCLK Setup Time
Full
IV
0.80
ns
tHSDI
SDI to
↑SCLK Hold Time
Full
IV
0.40
ns
tSSRFS
SRFS to
↓SCLK Setup Time
Full
IV
1.60
ns
tHSRFS
SRFS to
↓SCLK Hold Time
Full
IV
−0.13
ns
tSSTFS
STFS to
↓SCLK Setup Time
Full
IV
1.60
ns
tHSTFS
STFS to
↓SCLK Hold Time
Full
IV
−0.30
ns
tSSCS
SCS to
↑SCLK Setup Time
Full
IV
4.12
ns
tHSCS
SCS to
↑SCLK Hold Time
Full
IV
−2.76
ns
tDSDO
↑SCLK to SDO Delay Time
Full
IV
4.29
7.95
ns
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V and 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
3 SCLK rise/fall time should be 3 ns maximum.



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