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AD6654/PCB Folha de dados(PDF) 29 Page - Analog Devices |
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AD6654/PCB Folha de dados(HTML) 29 Page - Analog Devices |
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29 / 88 page  AD6654 Rev. 0 | Page 29 of 88 BALANCE 50 Ω SOURCE 25 Ω 100nF 25 Ω 100nF AD8351 INHI INLO RG OPHI OPLO VOCM 25 Ω 25 Ω DIGITAL OUT AD6654 AIN+ AIN– VREF 100nF Figure 40. ADC Driving Application Using Differential Input SINGLE- ENDED 50 Ω SOURCE R1 25 Ω 100nF 25 Ω 100nF AD8351 INHI INLO RG OPHI OPLO VOCM 25 Ω 25 Ω DIGITAL OUT AD6654 AIN+ AIN– VREF 100nF RF Figure 41. ADC Driving Application Using Single-Ended Input DDC CONFIGURATION NOTES PLL Clock Multiplier In the AD6654, the input clock rate must be the same as the input data rate. In a typical digital down-converter architecture, the clock rate is a limitation on the number of filter taps that can be calculated in the programmable RAM coefficient filters (MRCF, DRCF, and CRCF). For slower ADC clock rates (or for any clock rate), this limitation can be overcome by using a PLL clock multiplier to provide a higher clock rate to the RCF filters. Using this clock multiplier, the internal signal processing clock rate can be increased up to 200 MHz. The CLK signal is used as an input to the PLL clock multiplier. CLK PLL_CLK ADC_CLK DIVIDE BY N (1, 2, 4 OR 8) PLL CLOCK MULTIPLIER (4x TO 20x) PLL CLOCK GENERATION BYPASS_PLL 1 FOR BYPASS NM 2 5 0 1 1 0 Figure 42. PLL Clock Generation The PLL clock multiplier is programmable and uses the input clock rates between 30 MHz and 92.16 MHz to give a system clock rate (output) of as high as 200 MHz. The output clock rate is given by N M CLK CLK PLL × = _ where: CLK is the input port clock rate. M is a 5-bit programmable multiplication factor. N is a predivide factor and can be 1, 2, 4, or 8. M is a 5-bit number between 4 and 20 (inclusive). The multiplication factor, M, is programmed using a 5-bit PLL clock multiplier word in the ADC clock control register. A value outside the valid range of 4 to 20 bypasses the PLL clock multiplier and, therefore, the PLL clock is the same as the input clock. The predivide factor, N, is programmed using a 2-bit ADC pre-PLL clock divider word in the ADC clock control register, as listed in Table 13. Table 13. PLL Clock Generation Predivider Control Predivide Word [1:0] Divide-By Value for the Clock 00 Divide-by-1, bypass 01 Divide-by-2 10 Divide-by-4 11 Divide-by-8 For best signal processing advantage, the user should program the clock multiplier to give a system clock output as close as possible to, but not exceeding, 200 MHz. The internal blocks of the AD6654 that run off the PLL clock are rated to run at a maximum of 200 MHz. The default power-up state for the PLL clock multiplier is the bypass state, where CLK is passed on as the PLL clock. ADC Gain Control The DDC input port has individual, high speed gain control logic circuitry. Such gain control circuitry is useful in applica- tions that involve large dynamic-range inputs. The AD6654 gain control logic allows programmable upper and lower thresholds and a programmable dwell-time counter for temporal hysteresis. The DDC input port has a 3-bit output from the gain control block. The operation is controlled by the gain control enable bit in the gain control register of the DDC input port. Logic 1 in this bit programs the EXP[2:0] pins as gain control outputs. Function The gain control block features a programmable upper thresh- old register and a lower threshold register. The ADC input data is compared to both these registers. If ADC input data is larger than the upper threshold register, then the gain control output is decremented by 1. If the ADC input data is smaller than the lower threshold register, then the gain control output is incre- mented by 1. When decrementing the gain control output, the change is immediate. But when incrementing the output, a dwell-time register is used to delay the change. If the ADC input is larger than the upper threshold register value, the gain control output is immediately decremented to prevent overflow. When the ADC input is lower than the lower threshold register, a dwell timer is loaded with the value in the programmable 20-bit dwell-time register. The counter decrements once every |
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