AD6654SLASHPCB datasheet(81/88 Pages) AD

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AD6654

Rev. 0 | Page 81 of 88

CRCF Coefficient Memory

CRCF Memory. This memory has 64 words that have 20 bits

each. The memory contains the CRCF filter coefficients. The

data written to this memory space is 20-bit in twos complement

format. See the Channel RAM Coefficient Filter (CRCF) section

for the method to program the coefficients into the coefficient

memory.

AGC Control Register <10:0>

<10>: Channel Sync Select Bit. When this bit is set, the AGC

uses the sync signal from the channel for its synchronization.

When this bit is cleared, the SYNC pin used for synchronization

is defined by Bit 9 to Bit 8 of this register.

<9:8>: SYNC Pin Select Bits. When Bit 10 of this register is

cleared, these bits specify the SYNC pin used by AGC for

synchronization. These bits are don’t care when Bit 10 of the

AGC control register is set to Logic 1.

Table 39. SYNC Pin Select Bits

AGC Control Bits <9:8>

SYNC Pin Used by AGC

SYNC0

SYNC1

SYNC2

SYNC3

<7:5>: AGC Word Length Control Bits. These bits define the

word length of the AGC output. The output word can be 4 to 8,

10, 12, or 16 bits wide. Table 40 shows the possible selections.

Table 40. AGC Word Length Control Bits

AGC Control Bits <7:5>

Output Word Length (Bits)

000

001

010

011

100

101

110

111

<4>: AGC Mode Bit. When this bit is cleared, the AGC operates

to maintain a desired signal level. When this bit is set, it

operates to maintain a constant clipping level. See the

Automatic Gain Control section for details about these modes.

<3>: AGC Sync Now Bit. This bit is used to synchronize a

particular AGC, regardless of the channel, through the

programming ports (microport or serial port). When this bit is

set, the AGC block updates a new output sample (RSSI sample)

and starts working toward a new update sample.

<2>: Initialize on Sync Bit. This bit is used to determine

whether or not the AGC should initialize on a sync. When this

bit is set, during a synchronization the CIC filter is cleared and

new values for CIC decimation, number of averaging samples,

CIC scale, Signal Gain K, and the Pole P parameter are loaded.

When Bit 2 = 0, the above-mentioned parameters are not

updated, and the CIC filter is not cleared. In both cases, an

AGC update sample is output from the CIC filter and the

decimator starts operating towards the next output sample

whenever a sync occurs.

<1>: First Sync Only. This bit is used to ignore repetitive

synchronization signals. In some applications, the synchroniza-

tion signal occurs periodically. If this bit is cleared, each

synchronization request resynchronizes the AGC. If this bit is

set, only the first occurrence causes the AGC to synchronize

and updates the AGC gain values periodically, depending on

the decimation factor of the AGC CIC filter.

<0>: AGC Bypass Bit. When this bit is set, the AGC section is

bypassed. The N-bit representation from the interpolating half-

band filters is still reduced to a lower bit width representation as

set by Bit 7 to Bit 5 of the AGC control register. A truncation at

the output of the AGC accomplishes this task.

AGC Hold-Off Register <15:0>

The AGC hold-off counter is loaded with the value written to

this address when either a soft sync or pin sync comes into the

channel. The counter begins counting down. When it reaches 1,

a sync is sent to the AGC. This sync might or might not initial-

ize the AGC, as defined by the control word. The AGC loop is

updated with a new sample from the CIC filter whenever a sync

occurs. If this register is Logic 1, the AGC is immediately

updated when the sync occurs. If this register is Logic 0, the

AGC cannot be synchronized.

AGC Update Decimation <11:0>

This 12-bit register sets the AGC decimation ratio from 1 to

4096. An appropriate scaling factor should be set to avoid loss

of bits. The decimation ratio is given by the decimal value of the

AGC update decimation<11:0> register contents plus 1, that is,

12’0x000 describes a decimation ratio of 1, and 12’0xFFF

describes a decimation ratio of 4096.

AGC Signal Gain <11:0>

This register is used to set the initial value for a signal gain used

in the gain multiplier. This 12-bit value sets the initial signal

gain in the range of 0 dB and 96.296 dB in steps of 0.024 dB.

Initial signal gain (SG) in dB should be converted to a register

setting using the following formula:

⎥

⎦

⎤

⎢

⎣

⎡

256

)

(

log

round

Value

AGC Error Threshold <11:0>

This 12-bit register is the comparison value used to determine

which loop gain value (K1 or K2) to use for optimum operation.

When the magnitude-of-error signal is less than the AGC error

threshold value, then K1 is used; otherwise, K2 is used. The word

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