AD6654SLASHPCB datasheet(82/88 Pages) AD

82 / 88 page

AD6654

Rev. 0 | Page 82 of 88

format of the AGC error threshold register is four bits to the left

of the binary point and eight bits to the right.

See the Automatic Gain Control section for details.

256

)

(

log

⎥

⎦

⎤

⎢

⎣

⎡

Threshold

Error

round

Value

AGC Average Samples <5:0>

This 6-bit register contains the scale used for the CIC filter and

the number of power samples to be averaged before being sent

to the CIC filter.

<5:2>: CIC Scale. This 4-bit word defines the scale used for the

CIC filter. Each increment of this word increases the CIC scale

by 6.02 dB.

<1:0>: Number of AGC Average Samples. This defines the

number of samples to be averaged before they are sent to the

CIC decimating filter. See Table 41.

Table 41. Number of AGC Average Samples

AGC Average Samples <1:0>

Number of Samples Taken

AGC Pole Location <7:0>

This 8-bit register is used to define P, the open-loop filter pole

location. Its value can be set from 0 to 0.996 in steps of 0.0039.

This value of P is updated in the AGC loop each time the AGC

is initialized. This open-loop pole location directly impacts the

closed-loop pole locations, as explained in the Automatic Gain

Control section.

AGC Desired Level <7:0>

This register contains the desired signal level or desired clipping

level, depending on operational mode. This desired request

level (R) can be set in dB from 0 to 23.99 in steps of 0.094 dB.

The request level (R) in dB should be converted to a register

setting using the following formula:

⎥

⎦

⎤

⎢

⎣

⎡

)

(

log

round

Value

AGC Loop Gain 2 <7:0>

This 8-bit register is used to define K2, the second possible

open-loop gain. Its value can be set from 0 to 0.996 in steps of

0.0039. This value of K2 is updated each time the AGC is

initialized. When the magnitude-of-error signal in the loop is

greater than the AGC error threshold, then K2 is used by the

loop. K2 is updated only when the AGC is initialized.

AGC Loop Gain 1 <7:0>

This 8-bit register is used to define K1, the open-loop gain. Its

value can be set from 0 to 0.996 in steps of 0.0039. This value of

K is updated in the AGC loop each time the AGC is initialized.

When the magnitude-of-error signal in the loop is less than the

AGC error threshold, then K1 is used by the loop. K1 is updated

only when the AGC is initialized.

I Path Signature Register <15:0>

This 16-bit signature register is for the I path of the channel

logic. The signature register records data on the networks that

leave the channel logic, just before entering the second data

router.

Q Path Signature Register <15:0>

This 16-bit signature register is for the Q path of the channel

logic. The signature register records data on the networks that

leave the channel logic, just before entering the second data

router.

BIST Control <15:0>

<15>: Disable Signature Generation Bit. When this bit is active

high, the signature registers do not produce a pseudorandom

output value, but instead directly load the 24-bit input data.

When this bit is cleared, the signature register produces a

pseudorandom output for every clock cycle that it is active. See

the User-Configurable Built-In Self-Test (BIST) section for

details.

<14:0>: BIST Timer Bits. The <14:0> bits of this register form a

15-bit word that is loaded into the BIST timer. After loading the

BIST timer, the signature register is enabled for operation while

the timer is actively counting down. See the User-Configurable

Built-In Self-Test (BIST) section for details.

OUTPUT PORT REGISTER MAP

This part of the memory map deals with the output data and

controls for parallel output ports.

Parallel Port Output Control <23:0>

<23>: Port C Append RSSI Bit. When this bit is set, an RSSI

word is appended to every I/Q output sample, regardless of

whether the RSSI word is updated in the AGC. When this bit is

cleared, an RSSI word is appended to an I/Q output sample only

when the RSSI word is updated. The RSSI word is not output for

subsequent I/Q samples until the next time the RSSI is updated

in the AGC.

<22>: Port C, Data Format Bit. When this bit is set, the port is

configured for 8-bit parallel I/Q mode. When cleared, the port

is configured for 16-bit interleaved I/Q mode. See the Parallel

Port Output section for details.

<21>: Port C, AGC5 Enable Bit. When this bit is set, AGC5

data (I/Q data) is output on parallel Output Port C (data bus).

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