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COP8SCR9KMT7 Folha de dados(PDF) 14 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Nome de Peças COP8SCR9KMT7
Descrição Electrónicos  8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
PDF  80 Pages
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Fabricante Electrônico  NSC [National Semiconductor (TI)]
Página de início  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP8SCR9KMT7 Folha de dados(HTML) 14 Page - National Semiconductor (TI)

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8.0 Electrical Characteristics (Continued)
AC Electrical Characteristics (−40˚C
≤ T
A ≤ +85˚C) (Continued)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
Typ
Max
Units
Timer 1 Input High Time
1
t
C
Timer 1 Input Low Time
1
t
C
Timer 2, 3 Input High Time (Note 6)
1
MCLK or t
C
Timer 2, 3 Input Low Time (Note 6)
1
MCLK or t
C
Output Pulse Width
Timer 2, 3 Output High Time
150
ns
Timer 2, 3 Output Low Time
150
ns
USART Bit Time when using External
CKX
6 CKI
periods
µs
USART CKX Frequency when being
Driven by Internal Baud Rate Generator
2
MHz
Reset Pulse Width
1
t
C
tC = instruction cycle time.
Note 2: Maximum rate of voltage change must be < 0.5 V/ms.
Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 4: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F, G0,
and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to VCC; A/D converter and clock
monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins must
be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.
Note 7: Absolute Maximum Ratings should not be exceeded.
Note 8: VCC must be valid and stable before G6 is raised to a high voltage.
DC Electrical Characteristics (−40˚C
≤ T
A ≤ +125˚C)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
Typ
Max
Units
Operating Voltage
4.5
5.5
V
Power Supply Rise Time
10
50 x 10
6
ns
Power Supply Ripple (Note 2)
Peak-to-Peak
0.1 V
CC
V
Supply Current (Note 3)
High Speed Mode
CKI = 10 MHz
V
CC = 5.5V, tC = 0.5 µs
14.5
mA
CKI = 3.33 MHz
V
CC = 4.5V, tC = 1.5 µs
7
mA
Dual Clock Mode
CKI = 10 MHz, Low Speed OSC = 32 kHz
V
CC = 5.5V, tC = 0.5 µs
14.5
mA
CKI = 3.33 MHz, Low Speed OSC = 32 kHz
V
CC = 4.5V, tC = 1.5 µs
7
mA
Low Speed Mode
Low Speed OSC = 32 kHz
V
CC = 5.5V
65
110
µA
HALT Current with BOR Disabled (Note 4)
High Speed Mode
V
CC = 5.5V, CKI=0MHz
<440
µA
Dual Clock Mode
V
CC = 5.5V, CKI = 0 MHz, Low
Speed OSC = 32 kHz
<950
µA
Low Speed Mode
V
CC = 5.5V, CKI = 0 MHz, Low
Speed OSC = 32 kHz
<950
µA
Idle Current (Note 3)
High Speed Mode
CKI = 10 MHz
V
CC = 5.5V, tC = 0.5 µs
2.7
mA
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