COP8SCR9KMT7 datasheet(34/80 Pages) NSC

34 / 80 page

12.0 Timers

The device contains a very versatile set of timers (T0, T1, T2

and T3). Timers T1, T2 and T3 and associated autoreload/

capture registers power up containing random data.

12.1 TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE Timer T0, which is a

16-bit timer. The user cannot read or write to the IDLE Timer

T0, which is a count down timer.

As described in 13.0 Power Saving Features, the clock to the

IDLE Timer depends on which mode the device is in. If the

device is in High Speed mode, the clock to the IDLE Timer is

the instruction cycle clock (one-fifth of the CKI frequency). If

the device is in Dual Clock mode or Low Speed mode, the

clock to the IDLE Timer is the 32 kHz clock. For the remain-

der of this section, the term “selected clock” will refer to the

clock selected by the Power Save mode of the device.

During Dual Clock and Low Speed modes, the divide by 10

that creates the instruction cycle clock is disabled, to mini-

mize power consumption.

In addition to its time base function, the Timer T0 supports

the following functions:

•

Exit out of the Idle Mode (See Idle Mode description)

•

WATCHDOG logic (See WATCHDOG description)

•

Start up delay out of the HALT mode

•

Start up delay from BOR

Figure 15 is a functional block diagram showing the structure

of the IDLE Timer and its associated interrupt logic.

Bits 11 through 15 of the ITMR register can be selected for

triggering the IDLE Timer interrupt. Each time the selected

bit underflows (every 4k, 8k, 16k, 32k or 64k selected

clocks), the IDLE Timer interrupt pending bit T0PND is set,

thus generating an interrupt (if enabled), and bit 6 of the Port

G data register is reset, thus causing an exit from the IDLE

mode if the device is in that mode.

In order for an interrupt to be generated, the IDLE Timer

interrupt enable bit T0EN must be set, and the GIE (Global

Interrupt Enable) bit must also be set. The T0PND flag and

T0EN bit are bits 5 and 4 of the ICNTRL register, respec-

tively. The interrupt can be used for any purpose. Typically, it

is used to perform a task upon exit from the IDLE mode. For

more information on the IDLE mode, refer to 13.0 Power

Saving Features.

The Idle Timer period is selected by bits 0–2 of the ITMR

not be used as a software flag. Bits 4 through 7 of the ITMR

13.0 Power Saving Features.

TABLE 14. Idle Timer Window Length

ITSEL2

ITSEL1

ITSEL0

Idle Timer Period

High Speed

Mode

Dual Clock

Low Speed

Mode

4,096 inst.

cycles

0.125

seconds

8,192 inst.

cycles

0.25 seconds

16,384 inst.

cycles

0.5 seconds

32,768 inst.

cycles

1 second

65,536 inst.

cycles

2 seconds

Reserved - Undefined

ITSEL2

ITSEL1

ITSEL0

Idle Timer Period

High Speed

Mode

Dual Clock

Low Speed

Mode

Reserved - Undefined

The ITSEL bits of the ITMR register are cleared on Reset

and the Idle Timer period is reset to 4,096 instruction cycles.

12.1.1 ITMR Register

LSON

HSON

DCEN

CCK

SEL

RSVD ITSEL2 ITSEL1 ITSEL0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bits 7–4: Described in 13.0 Power Saving Features.

10138918

FIGURE 15. Functional Block Diagram for Idle Timer T0

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