COP8SCR9KMT7 datasheet(56/80 Pages) NSC

56 / 80 page

15.0 Interrupts (Continued)

15.4.2.1 Programming Example: External Interrupt

PSW

=00EF

CNTRL

=00EE

RBIT

0,PORTGC

RBIT

0,PORTGD

; G0 pin configured Hi-Z

SBIT

IEDG, CNTRL

; Ext interrupt polarity; falling edge

SBIT

GIE, PSW

; Set the GIE bit

SBIT

EXEN, PSW

; Enable the external interrupt

WAIT:

WAIT

; Wait for external interrupt

.=0FF

; The interrupt causes a

VIS

; branch to address 0FF

; The VIS causes a branch to

; interrupt vector table

.=01FA

; Vector table (within 256 byte

.ADDRW SERVICE

; of VIS inst.) containing the ext

; interrupt service routine

SERVICE:

; Interrupt Service Routine

RBIT,EXPND,PSW

; Reset ext interrupt pend. bit

RET I

; Return, set the GIE bit

15.5 PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake-up

circuitry. The register WKEN allows interrupts from Port L to

be individually enabled or disabled. The register WKEDG

specifies the trigger condition to be either a positive or a

negative edge. Finally, the register WKPND latches in the

pending trigger conditions.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart

execution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the

interrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wake-up information.)

15.6 INTERRUPT SUMMARY

The device uses the following types of interrupts, listed

below in order of priority:

The Software Trap non-maskable interrupt, triggered by

the INTR (00 opcode) instruction. The Software Trap is

acknowledged immediately. This interrupt service rou-

tine can be interrupted only by another Software Trap.

The Software Trap should end with two RPND instruc-

tions followed by a re-start procedure.

Maskable interrupts, triggered by an on-chip peripheral

block or an external device connected to the device.

Under ordinary conditions, a maskable interrupt will not

interrupt any other interrupt routine in progress. A

maskable interrupt routine in progress can be inter-

rupted by the non-maskable interrupt request. A

maskable interrupt routine should end with an RETI

instruction or, prior to restoring context, should return to

execute the VIS instruction. This is particularly useful

when exiting long interrupt service routines if the time

between interrupts is short. In this case the RETI instruc-

tion would only be executed when the default VIS rou-

tine is reached.

While executing from the Boot ROM for ISP or virtual E2

operations, the hardware will disable interrupts from oc-

curring. The hardware will leave the GIE bit in its current

state, and if set, the hardware interrupts will occur when

execution is returned to Flash Memory. Subsequent in-

terrupts, during ISP operation, from the same interrupt

source will be lost.

COP8SCR9KMT7 Folha de dados(PDF) 56 Page - National Semiconductor (TI)

COP8SCR9KMT7 Folha de dados(HTML) 56 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Folha de dados Download

Ligação URL