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COP8SCR9KMT7 Folha de dados(PDF) 76 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Nome de Peças COP8SCR9KMT7
Descrição Electrónicos  8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
PDF  80 Pages
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Fabricante Electrônico  NSC [National Semiconductor (TI)]
Página de início  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP8SCR9KMT7 Folha de dados(HTML) 76 Page - National Semiconductor (TI)

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21.0 Revision History
Date
Section
Summary of Changes
October 2000
Base revision for this history.
March 2001
Throughout
Various typographical errors.
General Description
Corrected I/O Pin count.
Ordering Information
Reformatted Part Numbering Scheme table.
Electrical Specifications
Reduced dynamic supply current specification.
Reduced input leakage current.
Clarified rise time restriction for high voltage on G6 pin.
Added general statement regarding specification limits.
Functional Description
Added table describing memory address ranges.
Clarified conditions causing erasure of the security bit.
In-System Programming
Clarified use of high voltage on G6 pin to force execution from Boot ROM.
Clarified interrupt activity when calling ISP routines in Boot ROM.
USART
Corrected table references in baud rate calculation example.
Development Support
Removed MetaLink office in Germany.
Corrected tools order information.
September 2001 General Description
Updated I/O Pins, Packages and Temperature.
Connection Diagrams
Added more packages, updated Pinouts table and Ordering Information.
Electrical Characteristics Added DC and AC Electrical for -40˚C to +125˚C temperature range.
USART
Clarified RCVG Operation.
Development Support
Updated with the latest support information.
Physical Dimensions
Added more package drawings.
January 2002
Forced Execution From
Boot ROM
Added figure.
April 2002
Connection Diagrams
Removed erroneous ADCH references in Pinout Table.
Pin Descriptions
Caution on GND connection on LLP package.
Timers
Clearification on high speed PWM Timer use.
Development Support
Updated with the latest support information.
February 2003
Pin Descriptions
Clarification of the functions of L4 and L6 for T2 and T3 PWM Output.
Reset
Addition of caution regarding rising edge on RESET with low V
CC.
Power Saving Features
Description of modified function of ITMR Register.
August 2003
Development Support
Updated with the latest support information.
Released as final.
www.national.com
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