COP8SCR9KMT7 datasheet(36/80 Pages) NSC

36 / 80 page

12.0 Timers (Continued)

12.2.3 Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin after

synchronization to the appropriate internal clock (t

MCLK). The Tx timer control bits, TxC3, TxC2 and TxC1

allow the timer to be clocked either on a positive or negative

edge from the TxA pin. Underflows from the timer are latched

into the TxPNDA pending flag. Setting the TxENA control flag

will cause an interrupt when the timer underflows.

In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB

control flag is set. The occurrence of a positive edge on the

TxB input pin is latched into the TxPNDB flag.

Figure 17 shows a block diagram of the timer in External

Event Counter mode.

Note: The PWM output is not available in this mode since the

TxA pin is being used as the counter input clock.

12.2.4 Mode 3. Input Capture Mode

The device can precisely measure external frequencies or

time external events by placing the timer block, Tx, in the

input capture mode. In this mode, the reload registers serve

as independent capture registers, capturing the contents of

the timer when an external event occurs (transition on the

timer input pin). The capture registers can be read while

maintaining count, a feature that lets the user measure

elapsed time and time between events. By saving the timer

value when the external event occurs, the time of the exter-

nal event is recorded. Most microcontrollers have a latency

time because they cannot determine the timer value when

the external event occurs. The capture register eliminates

the latency time, thereby allowing the applications program

to retrieve the timer value stored in the capture register.

In this mode, the timer Tx is constantly running at the fixed t

or MCLK rate. The two registers, RxA and RxB, act as

capture registers. Each register also acts in conjunction with

a pin. The register RxA acts in conjunction with the TxA pin

and the register RxB acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin after synchro-

nization to the appropriate internal clock (t

C or MCLK). Con-

trol bits, TxC3, TxC2 and TxC1, allow the trigger events to be

specified either as a positive or a negative edge. The trigger

condition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively latched into the

pending flags, TxPNDA and TxPNDB. The control flag

TxENA allows the interrupt on TxA to be either enabled or

disabled. Setting the TxENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

TxA pin. Similarly, the flag TxENB controls the interrupts

from the TxB pin.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the TxC0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the TxENA control flag. When a TxA interrupt

occurs in the Input Capture mode, the user must check both

the TxPNDA and TxC0 pending flags in order to determine

whether a TxA input capture or a timer underflow (or both)

caused the interrupt.

Figure 18 shows a block diagram of the timer T1 in Input

Capture mode. T2 and T3 are identical to T1.

12.3 TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

TxC3

Timer mode control

TxC2

Timer mode control

TxC1

Timer mode control

TxC0

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in Mode

3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

TxPNDB Timer Interrupt Pending Flag

10138920

FIGURE 17. Timer in External Event Counter Mode

10138921

FIGURE 18. Timer in Input Capture Mode

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