COP8SCR9KMT7 datasheet(24/80 Pages) NSC

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10.0 Functional Description

(Continued)

10.8 OSCILLATOR CIRCUITS

The device has two crystal oscillators to facilitate low power

operation while maintaining throughput when required. Fur-

ther information on the use of the two oscillators is found in

Section 7.0 Power Saving Features. The low speed oscillator

utilizes the L0 and L1 port pins. References in the following

text to CKI will also apply to L0 and references to G7/CKO

will also apply to L1.

10.8.1 Oscillator

CKI is the clock input while G7/CKO is the clock generator

output to the crystal. An on-chip bias resistor connected

between CKI and CKO is provided to reduce system part

count. The value of the resistor is in the range of 0.5M to 2M

(typically 1.0M). Table 2 shows the component values re-

quired for various standard crystal values. Resistor R2 is

on-chip, for the high speed oscillator, and is shown for

reference. Figure 12 shows the crystal oscillator connection

diagram. A ceramic resonator of the required frequency may

be used in place of a crystal if the accuracy requirements are

not quite as strict.

TABLE 2. Crystal Oscillator Configuration,

A = 25˚C, VCC =5V

R1 (k

Ω)R2 (MΩ)

C1 (pF)

C2 (pF)

CKI Freq.

(MHz)

On Chip

18–36

5.6

On Chip

100

100–156

0.455

020

32.768

kHz*

*Applies to connection to low speed oscillator on port pins L0 and L1 only.

**See Note below.

The crystal and other oscillator components should be

placed in close proximity to the CKI and CKO pins to mini-

mize printed circuit trace length.

The values for the external capacitors should be chosen to

obtain the manufacturer’s specified load capacitance for the

crystal when combined with the parasitic capacitance of the

trace, socket, and package (which can vary from 0 to 8 pF).

The guideline in choosing these capacitors is:

Manufacturer’s specified load cap = (C

1 *C2)/(C1 +C2)+

parasitic

2 can be trimmed to obtain the desired frequency. C2

should be less than or equal to C

Note: The low power design of the low speed oscillator

makes it extremely sensitive to board layout and load ca-

pacitance. The user should place the crystal and load ca-

pacitors within 1cm. of the device and must ensure that the

above equation for load capacitance is strictly followed. If

these conditions are not met, the application may have

problems with startup of the low speed oscillator.

TABLE 3. Startup Times

CKI Frequency

Startup Time

10 MHz

1–10 ms

3.33 MHz

3–10 ms

1 MHz

3–20 ms

455 kHz

10–30 ms

32 kHz (low speed oscillator)

2–5 sec

10.8.2 Clock Doubler

This device contains a frequency doubler that doubles the

frequency of the oscillator selected to operate the main

microcontroller core. The details of how to select either the

high speed oscillator or low speed oscillator are described in,

Power Saving Features. When the high speed oscillator

connected to CKI operates at 10 MHz, the internal clock

frequency is 20 MHz, resulting in an instruction cycle time of

0.5 µs. When the 32 kHz oscillator connected to L0 and L1 is

selected, the internal clock frequency is 64 kHz, resulting in

an instruction cycle of 152.6 µs. The output of the clock

doubler is called MCLK and is referenced in many places

within this document.

10138914

FIGURE 11. Reset Circuit Using Power-On Reset

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