| Os motores de busca de Datasheet de Componentes eletrônicos |
|
OPTION_REG Folha de dados(PDF) 101 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
OPTION_REG Folha de dados(HTML) 101 Page - Microchip Technology |
|
101 / 222 page ![]() 2013 Microchip Technology Inc. DS22331A-page 101 MCP19111 17.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a free running timer. The WDT is enabled by setting the WDTE bit of the Configuration Word (default setting). During normal operation, a WDT time-out generates a device Reset. If the device is in Sleep mode, a WDT time-out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by clearing the WDTE bit of the Configuration bit. See Section 12.1 “Configuration Word” for more information. 17.1 Watchdog Timer (WDT) Operation During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation; this is known as a WDT wake- up. The WDT can be permanently disabled by clearing the WDTE configuration bit. The postscaler assignment is fully under software control and can be changed during program execution. 17.2 WDT Period The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see Table 5-4). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. 17.3 WDT Programming Considerations Under worst-case conditions (i.e., VDD = Minimum, Temperature = Maximum, Maximum WDT prescaler), it may take several seconds before a WDT time-out occurs. FIGURE 17-1: WATCHDOG TIMER WITH SHARED PRESCALER BLOCK DIAGRAM T0CKI T0SE pin TMR0 Watchdog Timer WDT Time-out PS<2:0> Data Bus Set Flag bit T0IF on Overflow T0CS Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register. 2: WDTE bit is in the Configuration Word register. 0 1 0 1 0 1 8 8 8-bit Prescaler 0 1 FOSC/4 PSA PSA PSA Sync 2 TCY WDTE |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |