SPEAR1340 datasheet(32/200 Pages) STMICROELECTRONICS

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Device functions

SPEAr1340

32/200

Doc ID 023063 Rev 4

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Output FIFO: 16x32 bits

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Read scatter/gather list: 4x32 bits

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Write scatter/gather list: 4x32 bits

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Channel 3: Unified hash with HMAC (UHH)

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ID: 0x00004014

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Supported algorithms: HMAC MD5 (hash with 128-bit digest), HMAC SHA1 (hash

with 160-bit digest) and HMAC SHA2 (SHA256 and SHA224 with 256- and 224-bit

digest respectively)

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Input FIFO: 16x32 bits

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Output FIFO: 8x32 bits

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Channel 4: Unified hash 2 with HMAC (UHH2)

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ID: 0x00011001

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Supported algorithms: HMAC SHA384 (hash with 384-bit digest) and HMAC

SHA512 (hash with 512-bit digest)

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Input FIFO: 16x32 bits

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Output FIFO: 8x32 bits

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Channel 5: Public key accelerator (PKA) v6

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ID: 0x00006001

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Supported algorithms: modular exponentiation for RSA and Diffie-Hellman (up to

2048 bits), scalar multiplication of elliptic curve points over prime fields for ECC

(up to 384 bits) and Montgomery’s parameter for finite field operations

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Input FIFO: 8x32 bits

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Output FIFO: 8x32 bits

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Channel 6: Random number generator (RNG)

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ID: 0x0000F000

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Generates a sequence of true random numbers, based on a contiguous analog

oscillator; the sequence has a success ratio of more than 85 % for 20.000 bits,

according to FIPS 140-1 tests

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Monitors the entropy of the generated sequence

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Input FIFO: 2x32 bits

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Output FIFO: 4x32 bits

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Channel 7: empty

2.30

Real-time clock (RTC)

The RTC is a block that keeps track of the real time of day. It also functions as an alarm and

a calendar. The time is displayed in 24-hour format, and time/calendar values are stored in

binary-coded decimal format.

The time of day, alarm and calendar, status and control registers can all be accessed via a

standard 32 APB bus. All read/write operations last 2 cycles.

RTC provides a self-isolation mode that is activated during power down. This allows RTC to

continue its operation (except for the alarm interrupt feature that is not preserved) if power is

not supplied to the rest of the circuit. This feature is realized by supplying separate power

and clock connections.

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