SPEAR1340 datasheet(17/200 Pages) STMICROELECTRONICS

17 / 200 page

SPEAr1340

Device functions

Doc ID 023063 Rev 4

17/200

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Port Multiplier with command-based switching

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Disabling RX and TX Data clocks during power down modes

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Integrated SATA link layer and transport layer logic

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Supports PIO, first party and legacy DMA modes

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Supports legacy command queuing

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Supports ATA and ATAPI master-only emulation mode (for instance, register and

command compatible with these standards)

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Power-down mode

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Data scrambling

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CRC computation

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Automatic data flow control

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Far end loop-back re-timed

2.12

SATA/PCIe physical interface (MiPHY)

The MiPHY macrocell implements the lower (physical) layer protocols providing data

transmission and reception over a dual differential pair cable. The TX (transmit) and RX

(receive) serial channels operate plesiochronously (NRZ). The macrocell can be used in

Host or Device applications.

Main features:

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Serial transceiver (PHYsical layer) serializer and deserializer

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Direct support for 1.5/ 3.0 and 1.25/ 2.5/ 5.0 Gbit/s bit rates

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20-bit parallel interface

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Comma detect to provide word alignment of incoming serial stream

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SSC modulation

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Integrated impedance adaptation to transmission line characteristics

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Out-of-band (OOB) signaling

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Supported 1.2 V and 2.5 V power supply

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High-performance PLL (input reference 100 MHz for PCIe and 100 or 25 MHz for

SATA)

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Programmable TX buffer pre-emphasis, slew-rate and amplitude

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Dedicated TX buffer regulator for:

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Transmit buffer noise immunity

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Buffer level stability

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