SPEAR1340 datasheet(12/200 Pages) STMICROELECTRONICS

12 / 200 page

Device functions

SPEAr1340

12/200

Doc ID 023063 Rev 4

2.9

Giga/Fast Ethernet port (GMAC)

The GMAC IP provides the capability to transmit and receive data over Ethernet.

Main features:

●

Supports 10/100/1000 Mbps data transfer rates with the following PHY interfaces:

–

IEEE 802.3-compliant GMII/MII interface (default) to communicate with an external

Gigabit/Fast Ethernet PHY

–

RGMII interface to communicate with an external gigabit PHY

–

RMII interface (specification version 1.2 from RMII consortium) to communicate

with an external Fast Ethernet PHY (for 10/100 Mbps operations only)

●

Full-duplex operation:

–

IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on

flow control input de-assertion

–

Optional forwarding of received pause control frames to the user application

●

Half-duplex operation:

–

CSMA/CD Protocol support

–

Flow control using back-pressure support

–

Frame bursting and frame extension in 1000 Mbps half-duplex operation

●

Automatic CRC and pad generation controllable on a per-frame basis

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Provides options for automatic pad/CRC stripping on receive frames

●

Supports a variety of flexible address filtering modes, such as:

–

Up to 31 48-bit SA address comparison check with masks for each byte

–

64-bit hash filter for multicast and unicast (DA) addresses

–

Option to pass all multicast addressed frames

–

Promiscuous mode support to pass all frames without any filtering for network

monitoring

–

Passes all incoming packets (per filter) with a status report

●

Programmable frame length to support standard or jumbo Ethernet frames with up to

16 KB of size

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Programmable interframe gap (IFG) (40-96 bit times in steps of 8)

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Separate 32-bit status for transmit and receive packets

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IEEE 802.1Q VLAN tag detection for reception frames

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Self-managed DMA transfers with an internal DMA block

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Separate transmission, reception, and control interfaces to the application

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The host CPU uses a 32-bit AHB (AMBA 2.0) slave interface to access the GMAC

subsystem control and status registers (CSRs)

–

The GMAC transfers data to system memory through a 32-bit AXI (AMBA 3.0)

master interface

●

Support for network statistics with RMON/MIB counters (RFC2819/RFC2665)

●

A module for detection of LAN remote wake-up frames and AMD magic packet frames:

power management module (PMT)

●

A receive module for checksum off-load for received IPv4 and TCP packets

encapsulated by the Ethernet frame (Type 1)

●

An enhanced receive module for checking IPv4 header checksum and TCP, UDP, or

ICMP checksum encapsulated in IPv4 or IPv6 datagrams (Type 2)

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