SPEAR1340 datasheet(182/200 Pages) STMICROELECTRONICS

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Timing characteristics

SPEAr1340

182/200

Doc ID 023063 Rev 4

5.15.1

SPI master mode timings

SSP_SCK is the SPI output clock. The SSP_SCK frequency is programmable and derived

from PCLK, for details refer to the SSP section of the RM0078, Reference manual,

SPEAr1340 architecture and functionality.

Figure 43.

SPI master mode external timing waveform (SPH= 0, SPO =0 )

Table 95.

SPI master mode timing characteristics of SSP_SCK

Symbol

Parameters

Min

Max

Unit

TSSP_SCK

SSP_SCK clock period

Programmable

TSSP_SCK(H)

SSP_SCK clock high

pulse width

(TSSP_SCK/2) - 1 (TSSP_SCK/2) + 1

TSSP_SCK(L)

SSP_SCK clock low

pulse width

(TSSP_SCK/2) - 1 (TSSP_SCK/2) + 1

Table 96.

SPI master mode timing characteristics (SPH = 0, SPO=0)

Symbol

Parameters

Min

Max

Unit

TSU

Setup time, MISO (input) valid before

SSP_SCK (output) rising edge

Hold time, MISO (input) valid after SSP_SCK

(output) rising edge

TD1

Delay time, SSP_SS#n (output) falling edge to

first SSP_SCK (output) rising edge

TSSP_SCK-8

TSSP_SCK-2

TD2

Delay time, SSP_SCK (output) falling edge to

MOSI (output) transition

-4.64

12.4

TD3

Delay time, SSP_SCK (output) rising edge to

SSP_SS#n (output) rising edge

TSSP_SCK + 2 TSSP_SCK +8

DATA

MSB IN

LSB IN

LSB OUT

DATA

MSB OUT

SSP_SS#n

SSP_SCK

(SPO=0)

SSP_MISO

(input)

SSP_MOSI

(output)

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