SPEAR1340 datasheet(104/200 Pages) STMICROELECTRONICS

104 / 200 page

Pin description

SPEAr1340

104/200

Doc ID 023063 Rev 4

FSMC_AD21

Address bus

A21

FSMC_AD22

B21

FSMC_AD23

C21

FSMC_AD24

D21

FSMC_AD25

D22

FSMC_CE0n(1)

NAND/NOR/SRAM chip select (default NAND)

FSMC_CE1n

D11

FSMC_WEn

Write enable

FSMC_REn

Read enable

FSMC_ALE_AD17

Address latch enable /address pin #17

FSMC_CLE_AD16

Command latch enable / address pin #16

FSMC_RB0

NAND ready/busy[0] or NOR address valid or SRAM byte lane[0] (valid

only for 16-bit configuration)

FSMC_RSTPWDWN1 NAND ready/busy[1] or NOR reset power down[1]

A10

FSMC_RWPRT0n

NAND/NOR write protect [0] or SRAM byte lane[1] (valid only for 16-bit

configuration)

FSMC_RWPRT1n

NAND/NOR write protect [1]

E11

FSMC_RSTPWDWN0 NOR reset / Power down [0]

E10

FSMC_CE0n is used for booting from Parallel NOR or NAND Flash.

Table 11.

Memories - FSMC signals description (continued)

Signal name

Description

Type

Ball

Table 12.

Memories - SMI signals description

Signal name

Description

Type

Ball

SMI_DATAIN

Data in from external serial Flash

AB25

SMI_DATAOUT

Data out to external serial Flash

AB24

SMI_CLK

Data out clock to external Flash

AB28

SMI_CS0n(1)

Chip selects (active low)

AA27

SMI_CS1n

AB26

SMI_CS0n is used for booting from Serial NOR.

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