PIC12F508_09 datasheet(78/110 Pages) MICROCHIP

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PIC12F508/509/16F505

DS41236E-page 78

TABLE 10-5:

TIMING REQUIREMENTS – PIC12F508/509/16F505

FIGURE 10-6:

RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –

PIC12F508/509/16F505

CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

-40

°C ≤ TA ≤ +85°C (industrial)

-40

°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1 "Power-on Reset (POR)"

Param

No.

Sym.

Characteristic

Min.

Typ(1)

Max.

Units

TOSH2IOVOSC1

↑ (Q1 cycle) to Port Out Valid(2), (3)

——

100*

TOSH2IOIOSC1

↑ (Q2 cycle) to Port Input Invalid (I/O in hold time)(2)

—

TIOV2OSH

Port Input Valid to OSC1

↑ (I/O in setup time)

—

TIOR

Port Output Rise Time(3)

—10

25**

TIOF

Port Output Fall Time(3)

—10

25**

These parameters are characterized but not tested.

** These parameters are design targets and are not tested.

Note 1:

Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Measurements are taken in EXTRC mode.

See Figure 10-3 for loading conditions.

VDD

MCLR

Internal

POR

DRT

Timeout(2)

Internal

Reset

Watchdog

Timer

Reset

I/O pin(1)

Note

I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.

Runs in MCLR or WDT Reset only in XT, LP and HS (PIC16F505) modes.

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