PIC12F508_09 datasheet(31/110 Pages) MICROCHIP

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DS41236E-page 31

PIC12F508/509/16F505

5.0

I/O PORT

As with any other register, the I/O register(s) can be

written and read under program control. However, read

instructions (e.g., MOVF PORTB,W) always read the I/O

pins independent of the pin’s Input/Output modes. On

Reset, all I/O ports are defined as input (inputs are at

high-impedance) since the I/O control registers are all

set.

5.1

PORTB/GPIO

PORTB/GPIO is an 8-bit I/O register. Only the low-

order 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are

unimplemented and read as ‘0’s. Please note that RB3/

GP3 is an input only pin. The Configuration Word can

set several I/O’s to alternate functions. When acting as

alternate functions, the pins will read as ‘0’ during a port

read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4

can be configured with weak pull-ups and also for

wake-up on change. The wake-up on change and weak

pull-up functions are not pin selectable. If RB3/GP3/

MCLR is configured as MCLR, weak pull-up is always

on and wake-up on change for this pin is not enabled.

5.2

PORTC (PIC16F505 Only)

PORTC is an 8-bit I/O register. Only the low-order 6 bits

are used (RC<5:0>). Bits 7 and 6 are unimplemented

and read as ‘0’s.

5.3

TRIS Registers

The Output Driver Control register is loaded with the

contents of the W register by executing the TRIS f

instruction. A ‘1’ from a TRIS register bit puts the corre-

sponding output driver in a High-Impedance mode. A

‘0’ puts the contents of the output data latch on the

selected pins, enabling the output buffer. The excep-

tions are RB3/GP3, which is input only and the T0CKI

pin, which may be controlled by the OPTION register.

See Register 4-3 and Register 4-4.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon Reset.

5.4

I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-2. All port pins, except RB3/GP3 which is

input only, may be used for both input and output oper-

ations. For input operations, these ports are non-latch-

ing. Any input must be present until read by an input

instruction (e.g., MOVF PORTB, W). The outputs are

latched and remain unchanged until the output latch is

rewritten. To use a port pin as output, the correspond-

ing direction control bit in TRIS must be cleared (= 0).

For use as an input, the corresponding TRIS bit must

be set. Any I/O pin (except RB3/GP3) can be

programmed individually as input or output.

FIGURE 5-1:

PIC12F508/509/16F505

EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note:

On the PIC12F508/509, I/O PORTB is ref-

erenced as GPIO. On the PIC16F505, I/O

PORTB is referenced as PORTB.

Note:

On power-up, TOCKI functionality is

enabled in the OPTION register and must

be disabled to allow RC5 to be used as

general purpose I/O.

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

Data

Bus

Port

TRIS

‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

Reg

Latch

Reset

Note 1:

See Table 3-3 for buffer type.

VSS

VDD

(1)

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