EM357-RTR datasheet(48/240 Pages) ETC2

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EM351 / EM357

6.5.3

Further options for deep sleep

By default the low-frequency internal RC oscillator (OSCRC) is running during deep sleep (known as deep

sleep 1).

To conserver power, OSCRC can be turned of during deep sleep. This mode is known as deep sleep 2. Since the

OSCRC is disabled, the sleep timer and watchdog timer do not function and cannot wake the chip unless the

low-frequency 32.768 kHz crystal oscillator is used. Non-timer based wake sources continue to function. Once

a wake event does occur, OSCRC is restarted and comes back up.

6.5.4

Use of debugger with sleep modes

The debugger communicates with the EM35x using the SWJ.

When the debugger is logically connected, the CDBGPWRUPREQ bit in the debug port in the SWJ is set, and

the EM35x will only enter deep sleep 0 (the Emulated Deep Sleep state). The CDBGPWRUPREQ bit indicates

that a debug tool is logically connected to the chip and therefore debug state may be in the system debug

components. To maintain the debug state in the system debug components only deep sleep 0 may be used,

since deep sleep 0 will not cause a power cycle or reset of the core domain. The CSYSPWRUPREQ bit in the

debug port in the SWJ indicates that a debugger wants to access memory actively in the EM35x. Therefore,

whenever the CSYSPWRUPREQ bit is set while the EM35x is awake, the EM35x cannot enter deep sleep until

this bit is cleared. This ensures the EM35x does not disrupt debug communication into memory.

Clearing both CSYSPWRUPREQ and CDBGPWRUPREQ allows the EM35x to achieve a true deep sleep state (deep

sleep 1 or 2). Both of these signals also operate as wake sources, so that when a debugger logically connects

to the EM35x and begins accessing the chip, the EM35x automatically comes out of deep sleep. When the

debugger initiates access while the EM35x is in deep sleep, the SWJ intelligently holds off the debugger for a

brief period of time until the EM35x is properly powered and ready.

Note:

The SWJ-DP signals CSYSPWRUPREQ and CDBGPWRUPREQ are only reset by a power-on-reset or a

debugger. Physically connecting or disconnecting a debugger from the chip will not alter the state of these

signals. A debugger must logically communicate with the SWJ-DP to set or clear these two signals.

For more information regarding the SWJ and the interaction of debuggers with deep sleep, contact Ember

support for Application Notes and ARM® CoreSightTM documentation.

6-13

120-035X-000D

Preliminary

EM357-RTR Folha de dados(PDF) 48 Page - List of Unclassifed Manufacturers