EM357-RTR datasheet(98/240 Pages) ETC2

98 / 240 page

EM351 / EM357

8.6.4

RTS/CTS Flow control

RTS/CTS flow control, also called hardware flow control, uses two signals (nRTS and nCTS) in addition to

received and transmitted data (see Figure 8-5). Flow control is used by a data receiver to prevent buffer

overflow, by signaling an external device when it is and is not allowed to transmit.

Figure 8-5. RTS/CTS Flow Control Connections

The UART RTS/CTS flow control options are selected by the SC_UARTFLOW and SC_UARTAUTO bits in the

SC1_UARTCFG register (see Table 8-12). Whenever the SC_UARTFLOW bit is set, the UART will not start

transmitting a character unless nCTS is low (asserted). If nCTS transitions to the high state (deasserts) while a

character is being transmitted, transmission of that character continues until it is complete.

If the SC_UARTAUTO bit is set, nRTS is controlled automatically by hardware: nRTS is put into the low state

(asserted) when the receive FIFO has room for at least two characters, otherwise is it in the high state

(unasserted). If SC_UARTAUTO is clear, software controls the nRTS output by setting or clearing the

SC_UARTRTS bit in the SC1_UARTCFG register. Software control of nRTS is useful if the external serial device

cannot stop transmitting characters promptly when nRTS is set to the high state (deasserted).

Table 8-12. UART RTS/CTS Flow Control Configurations

SC1_UARTCFG

SC_UARTxxx

FLOW

AUTO

RTS

Pins Used

Operating Mode

TXD, RXD

No RTS/CTS flow control

0/1

TXD, RXD,

nCTS, nRTS

Flow control using RTS/CTS with software control of nRTS:

nRTS controlled by SC_UARTRTS bit in SC1_UARTCFG register

TXD, RXD,

nCTS, nRTS

Flow control using RTS/CTS with hardware control of nRTS:

nRTS is asserted if room for at least 2 characters in receive FIFO

1 The notation xxx means that the corresponding column header below is inserted to form the field name.

8.6.5

DMA

The DMA Channels section describes how to configure and use the serial receive and transmit DMA channels.

The receive DMA channel has special provisions to record UART receive errors. When the DMA channel

transfers a character from the receive FIFO to a buffer in memory, it checks the stored parity and frame error

status flags. When an error is flagged, the SC1_RXERRA/B register is updated, marking the offset to the first

received character with a parity or frame error. Similarly if a receive overrun error occurs, the SC1_RXERRA/B

registers mark the error offset. The receive FIFO hardware generates the INT_SCRXOVF interrupt and DMA

status register indicates the error immediately, but in this case the error offset is 4 characters ahead of the

8-27

120-035X-000D

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