EM357-RTR datasheet(132/240 Pages) ETC2

Nome de Peças	EM357-RTR

Descrição Electrónicos	High-Performance, Integrated ZigBee/802.15.4 System-on-Chip

PDF	240 Pages

Scroll/Zoom	100%

Fabricante Electrônico	ETC2 [List of Unclassifed Manufacturers]

Página de início

Logo

132 / 240 page

EM351 / EM357

Figure 9-16. Control Circuit in External Clock Mode 2

9.3.4

Capture/Compare Channels

Each capture/compare channel is built around a capture/compare register including a shadow register, an

input stage for capture with digital filter, multiplexing and prescaler, and an output stage with comparator

and output control.

Figure 9-17 gives an overview of the input stage of one capture/compare channel. The input stage samples the

corresponding TIy input to generate a filtered signal (TIyF). Then an edge detector with polarity selection

generates a signal (TIyFPy) which can be used either as trigger input by the slave mode controller or as the

capture command. It is prescaled before the capture register (ICyPS).

Figure 9-17. Capture/Compare Channel (Example: Channel 1 Input Stage)

The output stage generates an intermediate reference signal, OCyREF, which is only used internally. OCyREF is

always active high, but it may be inverted to create the output signal, OCy, that controls a GPIO output.

Figure 9-18 shows the basic elements of a capture/compare channel.

9-12

120-035X-000D

Preliminary

EM357-RTR Folha de dados(PDF) 132 Page - List of Unclassifed Manufacturers