HD64F2149YV datasheet(641/1075 Pages) RENESAS

641 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 613 of 1044

REJ09B0280-0300

HICR1 Bit 7—LPC Busy (LPCBSY): Indicates that the host interface is processing a transfer

cycle.

HICR1

Bit 7

LPCBSY

Description

Host interface is in transfer cycle wait state

(Initial value)

• Bus idle, or transfer cycle not subject to processing is in progress

• Cycle type or address indeterminate during transfer cycle

[Clearing conditions]

• LPC hardware reset or LPC software reset

• LPC hardware shutdown or LPC software shutdown

• Forced termination (abort) of transfer cycle subject to processing

• Normal termination of transfer cycle subject to processing

Host interface is performing transfer cycle processing

[Setting condition]

• Match of cycle type and address

HICR1 Bit 6—LCLK Request (CLKREQ): Indicates that the host interface’s SERIRQ output is

requesting a restart of LCLK.

HICR1

Bit 6

CLKREQ

Description

No LCLK restart request

(Initial value)

[Clearing conditions]

• LPC hardware reset or LPC software reset

• LPC hardware shutdown or LPC software shutdown

• SERIRQ is set to continuous mode

• There are no further interrupts for transfer to the host in quiet mode

LCLK restart request issued

[Setting condition]

• In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is

stopped

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