HD64F2149YV datasheet(642/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 614 of 1044

REJ09B0280-0300

HICR1 Bit 5—SERIRQ Busy (IRQBSY): Indicates that the host interface’s SERIRQ signal is

engaged in transfer processing.

HICR1

Bit 5

IRQBSY

Description

SERIRQ transfer frame wait state

(Initial value)

[Clearing conditions]

• LPC hardware reset or LPC software reset

• LPC hardware shutdown or LPC software shutdown

• End of SERIRQ transfer frame

SERIRQ transfer processing in progress

[Setting condition]

• Start of SERIRQ transfer frame

HICR1 Bit 4—LPC Software Reset Bit (LRSTB): Resets the host interface. For the scope of

initialization by an LPC reset, see section 18B.3.4, Host Interface Shutdown Function (LPCPD).

HICR1

Bit 4

LRSTB

Description

Normal state

(Initial value)

[Clearing conditions]

• Writing 0

• LPC hardware reset

LPC software reset state

[Setting condition]

• Writing 1 after reading LRSTB = 0

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