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HD64F2149YV Folha de dados(PDF) 640 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 640 Page - Renesas Technology Corp |
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640 / 1075 page  Section 18B Host Interface LPC Interface (LPC) Rev. 3.00 Jan 18, 2006 page 612 of 1044 REJ09B0280-0300 HICR0 Bit 2 HICR1 Bit 2 PMEE PMEB Description 0 0 PME output disabled, other function of pin P80 is enabled (Initial value) 1 PME output disabled, other function of pin P80 is enabled 1 0 PME output enabled, PME pin output goes to 0 level 1 PME output enabled, PME pin output is high-impedance HICR0 Bit 1—LSMI Output Enable (LSMIE) HICR1 Bit 1—LSMI Output Bit (LSMIB) These bits control LSMI output. LSMI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to V CC. When the LSMI output function is used, the DDR bit for PB0 must not be set to 1. HICR0 Bit 1 HICR1 Bit 1 LSMIE LSMIB Description 0 0 LSMI output disabled, other function of pin PB0 is enabled (Initial value) 1 LSMI output disabled, other function of pin PB0 is enabled 1 0 LSMI output enabled, LSMI pin output goes to 0 level 1 LSMI output enabled, LSMI pin output is high-impedance HICR0 Bit 0—LSCI Output Enable (LSCIE) HICR1 Bit 0—LSCI Output Bit (LSCIB) These bits control LSCI output. LSCI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to V CC. When the LSCI output function is used, the DDR bit for PB1 must not be set to 1. HICR0 Bit 0 HICR1 Bit 0 LSCIE LSCIB Description 0 0 LSCI output disabled, other function of pin PB1 is enabled (Initial value) 1 LSCI output disabled, other function of pin PB1 is enabled 1 0 LSCI output enabled, LSCI pin output goes to 0 level 1 LSCI output enabled, LSCI pin output is high-impedance |
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