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HD64F2149YV Folha de dados(PDF) 638 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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HD64F2149YV Folha de dados(HTML) 638 Page - Renesas Technology Corp

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Section 18B Host Interface LPC Interface (LPC)
Rev. 3.00 Jan 18, 2006 page 610 of 1044
REJ09B0280-0300
18B.2.2 Host Interface Control Registers 0 and 1 (HICR0, HICR1)
• HICR0
Bit
7
6
543
210
LPC3E
LPC2E
LPC1E
FGA20E SDWNE
PMEE
LSMIE
LSCIE
Initial value
0
0
000
000
Slave Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Host Read/Write
——
———
———
• HICR1
Bit
7
6
543
210
LPCBSY CLKREQ IRQBSY
LRSTB
SDWNB
PMEB
LSMIB
LSCIB
Initial value
0
0
000
000
Slave Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Host Read/Write
——
———
———
HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits
that determine pin output and the internal state of the host interface, and status flags that monitor
the internal state of the host interface.
HICR0 and HICR1 are initialized to H'00 by a reset and in hardware standby mode.
HICR0 Bits 7 to 5—LPC Enable 3 to 1 (LPC3E, LPC2E, LPC1E): These bits enable or disable
the host interface function in single-chip mode. When the host interface is enabled (at least one of
the three bits is set to 1), processing for data transfer between the slave processor and the host
processor is performed using pins LAD3 to LAD0,
LFRAME, LRESET, LCLK, SERIRQ,
CLKRUN, and LPCPD.
HICR0
Bit 7
LPC3E
Description
0
LPC channel 3 operation is disabled
(Initial value)
No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15
1
LPC channel 3 operation is enabled



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