HD64F2149YV datasheet(635/1075 Pages) RENESAS

635 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 607 of 1044

REJ09B0280-0300

18B.1.4 Register Configuration

Table 18B.2 lists the HIF:LPC registers.

Table 18B.2 Register Configuration

R/W

Name

Abbrevia-

tion

Slave

Host

Initial

Value

Slave

Address*

Host

Address*

System control register

SYSCR

R/W*

—

H'09

H'FFC4

—

System control register 2

SYSCR2

R/W

—

H'00

H'FF83

—

Host interface control

HICR0

R/W

—

H'00

H'FE40

—

Host interface control

HICR1

R/W

—

H'00

H'FE41

—

Host interface control

HICR2

R/W

—

H'00

H'FE42

—

Host interface control

HICR3

—

H'FE43

—

LADR3H

R/W

—

H'00

H'FE34

—

LPC channel 3 address

LADR3L

R/W

—

H'00

H'FE35

—

Input data register 1

IDR1

—

H'FE38

H'0060 and

H'0064

Output data register 1

ODR1

R/W

—

H'FE39

H'0060

Status register 1

STR1

R/(W)*

H'00

H'FE3A

H'0064

Input data register 2

IDR2

—

H'FE3C

H'0062 and

H'0066

Output data register 2

ODR2

R/W

—

H'FE3D

H'0062

Status register 2

STR2

R/(W)*

H'00

H'FE3E

H'0066

Input data register 3

IDR3

—

H'FE30

LADR3*

+0 and +4

Output data register 3

ODR3

R/W

—

H'FE31

LADR3*

5 +0

Status register 3

STR3

R/(W)*

H'00

H'FE32

LADR3*

5 +4

Two-way register 0MW

TWR0MW

—

H'FE20

LADR3*

+16 /–16

Two-way register 0SW

TWR0SW

—

H'FE20

LADR3*

+16 /–16

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