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ST70135 Folha de dados(PDF) 26 Page - STMicroelectronics

Nome de Peças ST70135
Descrição Electrónicos  ASCOTTM DMT TRANSCEIVER
PDF  29 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST70135 Folha de dados(HTML) 26 Page - STMicroelectronics

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ST70135A
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General purpose I/O register
2 general Purpose Register (0x040)
Bits from 3 to 15 are reserved
Reset Initialization
The ST70135A supports two reset modes:
– A ’hardware’ reset is activated by the RESETB
pin (active low). A hard reset occurs when a low
input value is detected at the RESETB input.
The low level must be applied for at least 1ms to
guarantee a correct reset operation. All clocks
and power supplies must be stable for 200ns
prior to the rising edge of the RESETB signal.
– ’Soft’ reset activated by the controller write
access to a soft reset configuration bit. The reset
process takes less than 10000 MCLK clock
cycles.
83
U_TxData_0
I
84
U_TxADDR_4
I
85
U_TxADDR_3
I
87
U_TxADDR_2
I
88
U_TxADDR_1
I
89
U_TxADDR_0
I
90
SLR_FRAME_F
92
SLR_FRAME_S
93
SLR_DATA_S_1
94
SLR_DATA_S_0
96
SLR_DATA_S
97
SLR_DATA_F_1
98
SLR_DATA_F_0
99
SLR_VAL_F
100
SLAP_CLOCK
101
SLT_FRAME_F
103
SLT_DATA_F_1
104
SLT_DATA_F_0
105
SLT_DATA_S_1
106
SLT_DATA_S_0
107
SLT_REQ_F
110
SLT_REQ_S
111
SLT_FRAME_S
112
TDI
113
TDO
114
TMS
116
TCK
118
TRSTB
119
TESTSE
none
120
GP_OUT
O
121
PDOWN
O
123
AFRXD_0
I
124
AFRXD_1
I
125
AFRXD_2
I
Table 6 : Boundary Scan Chain Sequence
Sequence
Number
Mnemonic
Pin
BS Type
126
AFRXD_3
I
128
CLWD
1
I
129
MCLK
1
C
130
CTRLDATA
1
O
132
AFTXED_0
O
133
AFTXED_1
O
135
AFTXED_2
O
136
AFTXED_3
O
138
IDDq
none
139
AFTXD_0
O
140
AFTXD_1
O
142
AFTXD_2
O
143
AFTXD_3
O
Field
Type
Position
Bits
Length
Function
GP_IN
R
[0,1]
2
Sampled
level on pins
GP_IN
GP_OUT
RW
[2]
1
Output level
on pins
GP_OUT
Table 6 : Boundary Scan Chain Sequence
Sequence
Number
Mnemonic
Pin
BS Type



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