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ST70135 Folha de dados(PDF) 22 Page - STMicroelectronics |
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ST70135 Folha de dados(HTML) 22 Page - STMicroelectronics |
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22 / 29 page ![]() ST70135A 22/29 The implementation must guarantee that all active SLR_Valid signals must be separated by at least 8 clock cycles. Refer to Figure 20. The SLR_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow. Transmit SLAP Interface The Transmit interface uses the following signals (refer to Figure 21): – SLT_REQ: byte request. – SLT_FRAME: start of frame indication. – SLT_DATA [1:0] data pins, a byte is transferred 2 bits at the time in 4 successive clock cycles. MSB first, odd bits on SLT_DATA [1]. The logical timing diagram is shown in Figure 22. The delay between Request and the associated data byte is defined as 8 cycles. The SLT_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow and guarantee that the frame indication is asserted when the first bits of the first DMT symbol are transferred. SLAP INTERFACE, AC Electrical Characteristics Figure 21 : Interface Towards PHY Layer Figure 22 : Interface Timing EXTERNAL CLOCK COMPONENT (SLAVE) MODEM (MASTER) REQUEST 2 DATA FRAME Tper Th Tl Thd Ts Td CLOCK ALL INPUTS ALL OUTPUTS Figure 23 : Transmit SLAP Interface Timing Diagram Symbol Parameter Test Conditi on Minimum Typical Maximum Unit Tper Clock Period Refer to MCLK ns Th Clock High 11 ns Tl Clock Low 11 ns Ts Setup 3 ns Thd Hold 2 ns Td Data Delay 20pF load 3 6 ns One byte in 4 cycles 01 89 1 CLOCK Undefined Undefined Request may be repeated b5 b3 b1 b4 b2 b0 b7 b6 SLT_DATA(0) SLT_FRAME 1 0 1 2 after 4 cycles Delay Request-data equals 8 cycles Repeated each superframe/ S-frame STM_CLOCK SLT_DATA(1) SLT_REQUEST |
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