ST70135 datasheet(14/29 Pages) STMICROELECTRONICS

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ST70135A

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DMT Symbol Timing Unit (DSTU)

The DSTU interfaces with various modules, like

DSP FrontEnd, FFT/IFFT, Mapper/Demapper, RS,

Monitor and Transceiver Controller. It consists of a

real time and a scheduler modules. The real time

unit generates a timebase for the DMT symbols

(sample counter), superframes (symbol counter)

and hyper-frames (sync counter). The timebases

can be modified by various control features. They

are continuously fine-tuned by the DPLL module.

The DSTU

schedulers execute a

program,

controlled by program opcodes and a set of

variables, the most important of which are real

time

counters.

The

transmit

and

receive

sequencers are completely independent and run

different

programs.

independent

set

variables is assigned to each of them. The

sequencer programs can be updated in real time.

ST70135A interfaces

Overview

See Figure 9.

Processor Interface (ATC)

The ST70135A is controlled and configured by an

external processor across the processor interface.

All programmable coefficients and parameters are

loaded through this path.

Data and addresses are multiplexed

ST70135A works in 16 bits data access, so

address bit 0 is not used. Address bit 1 is not

multiplexed with data. It has its own pin : BE1.

Byte access are not supported. Access cycle read

or write are always in 16 bits data wide, ie bit

address A0 is always zero value.

The interrupt request pin to the processor is INTB,

and is an Open Drain output.

The ST70135A supports both little and big endian.

The default feature is big endian.

Generic Interface

This interface is suitable for a number of

processors using a multiplexed Address/data bus.

In this case, synchronization of the input signals

with PCLK pin is not necessary.

Figure 9 : ST70135A Interfaces

AFE INTERFACE TO ADSL LINE (ST70134)

RESET

JTAG

CLOCK

PROCESSOR

INTERFACE

(ATC)

DIGITAL INTERFACE UTOPIA/BITSTREAM INTERFACE

ST70135A

Figure 10 : Generic Processor Interface Write Timing Cycle

Talew

Twr2cs

Tavs

Tavh

Tale2cs

Twr2d

Twdvd

Tdvh

Tcs2rdy

Tcs2wr

Twrw

Tmclk

Tcsre

Trdy2wr

ALE

CSB

AD(15-0)

WRB

READY

RDB

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