ST70135 datasheet(19/29 Pages) STMICROELECTRONICS

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ST70135A

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DIGITAL INTERFACE

Utopia Level 2 Interface

The ATM forum takes the ATM layer chip as a

reference. It defines the direction from ATM to

physical layer as the Transmit direction. The

direction from physical layer to ATM is the Receive

direction. Figure 17 shows the interconnection

between ATM and PHY layer devices, the optional

signals are not supported and not shown.

The UTOPIA interface transfers one byte in a

single clock cycle, as a result cells are transferred

in 53 clock cycles.Both transmit and receive

interfaces are synchronized on clocks generated

by the ATM layer chip, and no specific relationship

between Receive and Transmit clock is assumed,

they must be regarded as mutually asynchronous

clocks. Flow control signals are available to match

the bandwidth constraints of the physical layer

and the ATM layer. The UTOPIA level 2 supports

point to multipoint configurations by introducing

on addressing capability and by making a

distinction between polling and selecting a device:

– The ATM chip polls a specific physical layer chip

by putting its address on the address bus when

the Enb* line is asserted. The addressed physi-

cal layer answers the next cycle via the Clav line

reflecting its status at that time.

– The ATM chip selects a specific physical layer

by putting its address on the address bus when

the Enb* line is deasserted and asserting the

Enb* line on the next cycle. The addressed

physical layer chip will be the target or source of

the next cell transfer (see Figure 17).

Utopia Level 2 Signals

The physical chip sends cell data towards the

ATM layer chip. The ATM layer chip polls the

status of the fifo of the physical layer chip. The cell

exchange proceeds like:

a) The physical layer chip signals the availability

of a cell by asserting RxClav when polled by

the ATM chip.

b) The ATM chips selects a physical layer chip,

then starts the transfer by asserting RxEnb*.

If the physical layer chip has data to send, it

puts them on the RxData line the cycle after it

sampled RxEnb* active. It also advances the

offset in the cell. If the data transferred is the

first byte of a cell, RxSOC is 1b at the time of

the data transfer, 0b otherwise.

The ATM chip accepts the data when they are

available. If RxSOC was 1b during the transfer,

it resets its internal offset pointer to the value 1,

otherwise it advances the offset in the cell.

ST70135A Utopia Level 2 MPHY Operation

Utopia level 2 MPHY operation can be done by

various

interface

schemes.

The

ST70135A

supports only the required mode, this mode is

referred to as ”Operation with 1 TxClav and 1

RxClav”.

PHY Device Identification

The ST70135A holds 2 PHY layer Utopia ports,

one is dedicated to the fast data channel, the

other one to the interleaved data channel. The

associated PHY address is specified by the

PHY_ADDR_x fields in the Utopia PHY address

Figure 17 : Signal at Utopia Level 2 Interface

PHY

RECEIVE

RxADDR

RxCLAV

RxENB*

RxCLK

RxDATA

RxSOC

PHY

ATM

RxREF*

ATM

RECEIVE

PHY

TRANSMIT

TxADDR

TxCLAV

TxENB*

TxCLK

TxDATA

TxSOC

TxREF*

ATM

TRANSMIT

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