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ST70135 Folha de dados(PDF) 25 Page - STMicroelectronics

Nome de Peças ST70135
Descrição Electrónicos  ASCOTTM DMT TRANSCEIVER
PDF  29 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST70135 Folha de dados(HTML) 25 Page - STMicroelectronics

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Tests, Clock, JTAG Interface
– Mclk: Master Clock (35.328MHz) generated by
VCXO
– ATM receive interface, asynchronous clock gen-
erated by Utopia Master
– ATM transmit interface, asynchronous clock
generated by Utopia Master
– ATC clock (Pclk): external asynchronous clock
(synchronous with ATC in case of i960 specific
interface)
JTAG TP interface: Standard Test Access Port,
Used with the boundary scan for chip and board
testing. This JTAG TAP interface consists in 5
signals:
TDI, TDO, TCK & TMS.
TSRTB: Test Reset, reset the TAP controller.
TRSTB is an active low signal.
Table 6 : Boundary Scan Chain Sequence
Sequence
Number
Mnemonic
Pin
BS Type
2
AD_0
B
3
AD_1
B
4
AD_2
B
6
AD_3
B
7
AD_4
B
9
AD_5
B
10
AD_6
B
12
AD_7
B
13
AD_8
B
14
AD_9
B
16
AD_10
B
17
AD_11
B
19
AD_12
B
21
PCLK
I
23
AD_13
B
24
AD_14
B
25
AD_15
B
27
BE1
I
28
ALE
C
30
CSB
I
31
WR_RDB
I
32
RDYB
O
33
OBC_TYPE
I
34
INTB
O
35
RESETB
I
38
U_RxData_0
B
39
U_RxData_1
B
41
U_RxData_2
B
42
U_RxData_3
B
44
U_RxData_4
B
45
U_RxData_5
B
46
VSS
47
U_RxData_6
B
48
U_RxData_7
B
50
U_RxADDR_0
I
51
U_RxADDR_1
I
52
U_RxADDR_2
I
53
U_RxADDR_3
I
55
U_RxADDR_4
I
56
GP_IN_0
i
58
GP_IN_1
I
60
U_RxRefB
O
61
U_TxRefB
I
63
U_RxCLK
64
U_RxSOC
65
U_RxCLAV
66
U_RxENBB
68
U_TxCLK
69
U_TxSOC
70
U_TxCLAV
71
U_TxENBB
74
U_TxData_7
I
75
U_TxData_6
I
77
U_TxData_5
I
78
U_TxData_4
I
79
U_TxData_3
I
80
U_TxData_2
I
82
U_TxData_1
I
Table 6 : Boundary Scan Chain Sequence
Sequence
Number
Mnemonic
Pin
BS Type



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