ST70135 datasheet(10/29 Pages) STMICROELECTRONICS

10 / 29 page

ST70135A

10/29

= Input, CMOS levels

I-PU

= Input with pull-up resistance, CMOS

levels

I-PD

= Input

with

pull-down

resistance,

CMOS levels

I-TTL

= Input TTL levels

= Push-pull output

= Push-pull output with high-impedance

state

= Input / Tristate Push-pull output

BS cell = Boundary-Scan cell

= Input cell

= Output cell

= Bidirectional cell

= Clock

Main Block Description

The following drawings describe the sequence of

functions performed by the chip.

DSP Front-End

The DSP Front-End contains 4 parts in the

receive direction: the Input Selector, the Analog

Front-End Interface, the Decimator and the Time

Equalizer. The input selector is used internally to

enable test loopbacks inside the chip. The Analog

Front-End

lnterface

transfers

16-bit

words,

multiplexed on 4 input/output signals. Word

transfer is carried out in 4 clock cycles.

The Decimator receives 16-bit samples at 8.8MHz

(as sent by the Analog Front-End chip: ST70134)

and reduces this rate to 2.2MHz.

The Time Equalizer (TEQ) module is a FIR filter

with programmable coefficients. Its main purpose

reduce

the

effect

Inter-Symbol

Interferences (ISI) by shortening the channel

impulse response. Both the Decimator and TEQ

can be bypassed. In the transmit direction, the

DSP

Front-End

includes:

sidelobe

filtering,

clipping, delay equalization and interpolation. The

sidelobe filtering and delay equalization are

implemented by IIR Filters, reducing the effect of

echo in FDM systems. Clipping is a statistical

process limiting the amplitude of the output signal,

optimizing the dynamic range of the AFE. The

interpolator

receives

data

2.2MHz

and

generates samples at a rate of 8.8MHz.

DMT Modem

This module is a programmable DSP unit. Its

instruction set enables the basic functions of the

DMT algorithm like FFT, IFFT, Scaling, Rotor and

Frequency Equalization (FEQ) in compliance with

ANSI T1.413 specifications.

In the RX path, the 512-point FFT transforms the

time-domain DMT

symbol into

a frequency

domain representation which can be further

decoded by the subsequent demapping stages.

In other words, the Fast Fourier Transform process

is used to transform from time domain to frequency

domain (receive path). 1024 time samples are

processed. After the first stage time domain

equalization and FFT block an ICI (InterCarrier

Interference) free information stream turns out.

Figure 3 : DSP Front-End Receive

Figure 4 : DSP Front-End Transmit

From

Analog

Front-end

SELECT

AFE

I/F

DEC

TEC

BYPASS

To DMT

Modem

From

DMT

Modem

FILTERING

CLIPPING

AFE

I/F

To Analog

Front End

DELAY

EQUALIZER

OUT

SELECT

INTER-

POLATOR

ST70135 Folha de dados(PDF) 10 Page - STMicroelectronics

ST70135 Folha de dados(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Folha de dados Download

Ligação URL