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ST70135 Folha de dados(PDF) 24 Page - STMicroelectronics |
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ST70135 Folha de dados(HTML) 24 Page - STMicroelectronics |
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24 / 29 page ![]() ST70135A 24/29 Figure 26 : Transmit Interface Table 1 : Transmitted Bits Assigned to Signal / Time Slot Figure 27 : Receive Interface MCLK AFTXD CLWD Tv Tc AFTXED MCLK AFRXD Ts Th Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFTXD[0] b0 b4 b8 b12 AFTXD[1] b1 b5 b9 b13 AFTXD[2] b2 b6 b10 b14 AFTXD[3] b3 b7 b11 b15 GP_OUT t0 t1 t2 t3 Table 2 : Transmitted Bits Assigned to Signal / Time Slot Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFRXD[0] b0 b4 b8 b12 AFRXD[1] b1 b5 b9 b13 AFRXD[2] b2 b6 b10 b14 AFRXD[3] b3 b7 b11 b15 GP_IN t0 t1 t2 t3 Table 3 : Master Clock (MCLK) AC Electrical Characteristics Symbol Parameter Minimum Typical Maximum Unit F Clock Frequency 35.328 MHz Tper Clock Period 28.3 ns Th Clock Duty Cycle 40 60 % Table 4 : AFTXD, AFTXED, CLWD AC Electrical Characteristics Symbol Parameter Minimum Typical Maximum Unit Tv Data Valid Time 0 10 ns Tc Data Valid Time 0 10 ns Table 5 : AFRXD AC Electrical Characteristics Symbol Parameter Minimum Typical Maximum Unit Ts Data setup Time 5 ns Th Data hold Time 5 ns |
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