ST70135A

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Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable

(tri-state) all outputs of the Utopia interface. It is enabled by the TRI_STATE_EN bit in the Rx_interface

control register.

Pin Description Utopia 2 (Receive Interface)

*Active low signal

Pin Description Utopia 2 (Transmit interface)

*Active low signal

Name

Type

Meaning

Usage

Remark

RxClav

O

Receive Cell available

Signals to the ATM chip that

the STLC60135 has a cell

ready for transfer

Remains active for the entire

cell transfer

RxEnb*

I

Receive Enable

Signals to the physical layer

that the ATM chip will sample

and accept data during next

clock cycle

RxData and RxSOC could be

tri-state when RxEnb* is

inactive (high)

RxClk

I

Receive Byte Clock

Gives the timing signal for the

transfer, generated by ATM

layer chip.

RxData

O

Receive Data (8 bits)

ATM cell data, from physical

layer chip to ATM chip, byte

wide.

RxSOC

O

Receive Start Cell

Identifies the cell boundary on

RxData

Indicate to the ATM layer chip

that RxData contains the first

valid byte of a cell.

RxAddr

I

Receive Address (5 bits)

Use to select the port that will

be active or polled

RxRef *

O

Reference Clock

8kHz clock transported over

the network

Name

Type

Meaning

Usage

Remark

TxClav

O

Transmit Cell available

Signals to the ATM chip that the

physical layer chip is ready to

accept a cell

Remains active for the entire

cell transfer

TxEnb*

I

Transmit Enable

Signals to the physical layer

that TxData and TxSOC are

valid

TxClk

I

Transmit Byte Clock

Gives the timing signal for the

transfer, generated by ATM

layer chip.

TxData

I

Transmit Data (8 bits)

ATM cell data, to physical layer

chip to ATM chip, byte wide.

TxSOC

I

Transmit Start of Cell

Identifies the cell boundary on

TxData

TxAddr

I

Transmit Address (5 bits)

Use to select the port that will

be active or polled

TxRef *

I

Reference Clock

8kHz clock from the ATM layer

chip