| Os motores de busca de Datasheet de Componentes eletrônicos |
|
TUSB8042AI Folha de dados(PDF) 13 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TUSB8042AI Folha de dados(HTML) 13 Page - Texas Instruments |
|
13 / 64 page ![]() over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD33_2H_ 0SS_4HS VDD33 current upstream port connected to USB 2.0 Host, downstream port(s) connected to 0 SS devices, and 4 HS device. VDD = 1.1V; VDD33 = 3.3V; TA = 25°C; 76 mA 3.3V I/O VIH High-level input voltage(1) 2 3.6 V VIL Low-level input voltage(1) 0 0.8 V VI Input voltage 0 3.6 V VO Output voltage(2) 0 3.6 V tt Input transition time (tRISE and tFALL) 25 ns VHYS Input hysteresis(3) 0.13 x VDD33 V VOH High-level output voltage IOH = –4 mA 2.4 V VOL Low-level output voltage IOH = 4 mA 0.4 V IOZP High-impedance output current with internal pullup or pulldown resistor.(4) VI = 0 to VDD33; –250 250 µA II Input current(5) VI = 0 to VDD33; –15 15 µA RPD Internal pulldown resistance 13.5 19 27.5 kΩ RPU Internal pullup resistance 14.5 19 25 kΩ (1) Applies to external inputs and bidirectional buffers (2) Applies to external outputs and bidirectional buffers (3) Applies to GRSTZ (4) Applies to pins with internal pullups/pulldowns. (5) Applies to external input buffers 6.6 Timing Requirements MIN NOM MAX UNIT Power-on timings. Refer to Figure 6-1 td1 VDD stable before VDD33 stable. (2) (3) 0 ms td2 VDD and VDD33 before deassertion of GRSTz. 3 ms tsu_io Setup for MISC inputs. (1) 0.1 µs thd_io Hold for MISC inputs. (1) 0.1 µs tVDD33_RAM P VDD33 supply ramp requirement. 0.2 100 ms tVDD_RAMP VDD supply ramp requirement. 0.2 100 ms (1) MISC pins sampled at deassertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL. (2) As long as GRSTz is deasserted after both supplies are stable, there is no power-on relationship between VDD33 and VDD. If GRSTz is only connected to a capacitor to GND, then VDD must be stable minimum of 10 µs before VDD33. (3) An active reset is required if the VDD33 supply is stable before VDD supply. This active reset shall meet the 3 ms power-up delay counting from both power supplies stable to deassertion of GRSTz. www.ti.com TUSB8042A SLLSF93A – JUNE 2019 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TUSB8042A |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |