TUSB8042AI datasheet(49/64 Pages) TI2

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9.3.3 Ground

TI recommends that only one board ground plane be used in the design. This provides the best image plane for

signal traces running above the plane. TI recommends to connect the thermal pad of the TUSB8042A and any

of the voltage regulators to the ground plane with vias. An earth or chassis ground is implemented only near the

USB port connectors on a different plane for EMI and ESD purposes.

9.4 Layout

9.4.1 Layout Guidelines

9.4.1.1 Placement

1. Place the 9.53K ±1% resistor connected to pin USB_R1 as close as possible to the TUSB8042A.

2. Place a 0.1µF capacitor as close as possible on each VDD and VDD33 power pin.

3. Place the 100nF capacitors on the SSTXP and SSTXM nets close to the USB connector (Type-A, Type-B,

and so forth).

4. Place ESD and EMI protection devices (if used) as close as possible to the USB connector.

5. If a crystal is used, place the crystal as close as possible to the TUSB8042A XI and XO pins.

6. Place voltage regulators as far away from the TUSB8042A, the crystal, and the differential pairs as possible.

7. In general, place the large bulk capacitors associated with each power rail as close to the voltage regulators

as possible.

9.4.1.2 Package Specific

1. The TUSB8042A package has a 0.5mm pin pitch.

2. The TUSB8042A package has a 6.0mm × 6.0mm thermal pad. This thermal pad must be connected to

ground through a system of vias.

3. TI recommends to solder mask all vias under device, except for those connected to thermal pad, to avoid

any potential issues with thermal pad layouts.

9.4.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB8042A differential pairs: USB_DP_XX,

USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.

1. Must be designed with a differential impedance of 90Ω ±10%.

2. To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Separate each pair

by at least 5 times the signal trace width. Separating with ground as depicted in the layout example also

helps minimize crosstalk.

3. Route all differential pairs on the same layer adjacent to a solid ground plane.

4. Do not route differential pairs over any plane split.

5. Adding test points causes impedance discontinuity, and therefore negative impacts signal performance. If

test points are used, place the points in series and symmetrically. The test paints must not be placed in a

manner that causes stub on the differential pair.

6. Avoid 90 degree turns in trace. Keep the use of bends in differential traces to a minimum. When bends are

used, make sure the number of left and right bends are as equal as possible and the angle of the bend is ≥

135 degrees. This minimizes any length mismatch causes by the bends and therefore minimize the impact

bends have on EMI.

7. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for SS

differential pair signals and USB 2.0 differential pair signals is eight inches. Longer trace lengths require very

careful routing to ensure proper signal integrity.

8. Match the etch lengths of the differential pair traces (that is, DP and DM or SSRXP and SSRXM or SSTXP

and SSTXM). Make sure there is less than a 5mil difference between a SS differential pair signal and the

complement. Make sure the USB 2.0 differential pairs do not exceed 50 mils relative trace length difference.

9. The etch lengths of the differential pair groups do not need to match (that is, the length of the SSRX pair to

that of the SSTX pair), but make sure to minimize all trace lengths.

10. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure

that the same via type and placement are used for both signals in a pair. If any vias are used, place the vias

as close to the TUSB8042A device as possible.

www.ti.com

TUSB8042A

SLLSF93A – JUNE 2019 – REVISED JANUARY 2025

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