TUSB8042AI datasheet(21/64 Pages) TI2

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7.3.5 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12pF to 24pF and frequency stability rating

of ±100PPM or better. To ensure proper start-up oscillation condition, a maximum crystal equivalent series

resistance (ESR) of 50Ω is recommended. Use a parallel load capacitor if a crystal source is used. The exact

load capacitance value used depends on the crystal vendor. Refer to the Selection and Specification for Crystals

for Texas Instruments USB2.0 Devices application note for details on how to determine the load capacitance

value.

7.3.6 Input Clock Requirements

When using an external clock source such as an oscillator, make sure the reference clock has ±100PPM or

better frequency stability, less than 50ps absolute peak-to-peak jitter, or less than 25ps peak-to-peak jitter after

applying the USB 3.2 Gen1 jitter transfer function. TI recommends to tie XI to the 1.8V clock source and to leave

the XO floating.

7.3.7 Power-Up and Reset

The TUSB8042A does not have specific power sequencing requirements with respect to the core power (VDD)

or I/O and analog power (VDD33) as long as GRSTz is held in an asserted state while supplies ramp. The core

power (VDD) or I/O power (VDD33) can be powered up for an indefinite period of time while the other is not

powered up if all of these constraints are met:

• All maximum ratings and recommended operating conditions are observed.

• All warnings about exposure to maximum rated and recommended conditions are observed, particularly

junction temperature. These apply to power transitions as well as normal operation.

• Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the

device.

• Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. The supply bus is

powered down when the voltage is below that range, either stable or in transition.

A minimum reset duration of 3ms is required. This is defined as the time when the power supplies are in the

recommended operating range to the deassertion of GRSTz. This can be generated using programmable-delay

supervisory device or using an RC circuit. When a RC circuit is used, the external capacitor size chosen must be

large enough to meet the 3ms minimum duration requirement. The R of the RC circuit is the internal RPU.

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TUSB8042A

SLLSF93A – JUNE 2019 – REVISED JANUARY 2025

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