TUSB8042AI datasheet(28/64 Pages) TI2

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8.7 Device Configuration Register

Figure 8-6. Register Offset 5h

Bit No.

Reset State

Note

Reset state of REG_05h[1] for TUSB8042A is 0 and for TUSB8042A1 is 1.

Table 8-7. Bit Descriptions – Device Configuration Register

Bit

Field

Type

Description

customStrings

Custom strings enable. This bit controls the ability to write to

the Manufacturer String Length, Manufacturer String, Product String

Length, Product String, and Language ID registers

0 = The Manufacturer String Length, Manufacturer String, Product

String Length, Product String, and Language ID registers are read only

1 = The Manufacturer String Length, Manufacturer String, Product

String Length, Product String, and Language ID registers can be

loaded by EEPROM or written by SMBus

The default value of this bit is 0.

customSernum

Custom serial number enable. This bit controls the ability to write to the

serial number registers.

0 = The Serial Number String Length and Serial Number String

registers are read only

1 = Serial Number String Length and Serial Number String registers

can be loaded by EEPROM or written by SMBus

The default value of this bit is 0.

u1u2Disable

U1 U2 Disable. This bit controls the U1/U2 support.

0 = U1/U2 support is enabled

1 = U1/U2 support is disabled

When U1/U2 support is disabled, the TUSB8042A does not initiate or

accept any U1 or U2 requests on any port, upstream or downstream,

unless the device receives or sends a Force_LinkPM_Accept LMP.

After receiving or sending an FLPMA LMP, the device continues to

enable U1 and U2 according to USB 3.2 protocol until the device gets a

power-on reset or is disconnected on the upstream port.

When the TUSB8042A is in I2C mode, the TUSB8042A loads this bit

from the contents of the EEPROM.

When the TUSB8042A is in SMBUS mode, the value can be

overwritten by an SMBus host.

RSVD

Reserved. This bit is reserved and returns 1 when read.

ganged

Ganged. This bit is loaded at the deassertion of reset with the value of

the GANGED/SMBA2/HS_UP pin.

0 = When fullPwrMgmtz = 0, each port is individually power switched

and enabled by the PWRCTL[4:1]/BATEN[4:1] pins

1 = When fullPwrMgmtz = 0, the power switch control for all ports is

ganged and enabled by the PWRCTL[4:1]/BATEN1 pin

When the TUSB8042A is in I2C mode, the TUSB8042A loads this bit

from the contents of the EEPROM.

When the TUSB8042A is in SMBUS mode, the value can be

overwritten by an SMBus host.

fullPwrMgmtz

Full Power Management. This bit is loaded at the deassertion of reset

with the value of the FULLPWRMGMTz/SMBA1/SS_UP pin.

0 = Port power switching status reporting is enabled

1 = Port power switching status reporting is disabled

When the TUSB8042A is in I2C mode, the TUSB8042A loads this bit

from the contents of the EEPROM.

When the TUSB8042A is in SMBUS mode, the value can be

overwritten by an SMBus host.

TUSB8042A

SLLSF93A – JUNE 2019 – REVISED JANUARY 2025

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