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Document number: BST-BMP280-DS001-26 Revision_1.26_102021

Start RW

Stop

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CSB

Data byte

Data register - address F7h

CSB

Control byte

Data byte

Data register - address F6h

Figure 11: SPI multiple byte read

5.4 Interface parameter specification

5.4.1

General interface parameters

The general interface parameters are given in Table 26 below.

Table 26: interface parameters

Parameter

Symbol

Condition

Min

Typ

Max

Units

Input – low level

Vil_si

VDDIO=1.2V to 3.6V

0.2 *

VDDIO

Input – high level

Vih_si

VDDIO=1.2V to 3.6V

0.8 *

VDDIO

Output – low level for I2C Vol_SDI VDDIO=1.62V, iol=3 mA

0.2 *

VDDIO

Output – low level for I2C Vol_SDI

_1.2

VDDIO=1.20V, iol=3 mA

0.23 *

VDDIO

Output – low level

Vol_SD

VDDIO=1.62V, iol=1 mA

0.2 *

VDDIO

Output – low level

Vol_SD

O_1.2

VDDIO=1.20V, iol=1 mA

0.23 *

VDDIO

Output – high level

Voh

VDDIO=1.62V, ioh=1 mA

(SDO, SDI)

0.8 *

VDDIO

Output – high level

Voh_1.2 VDDIO=1.2V, ioh=1 mA

(SDO, SDI)

0.6 *

VDDIO

Pull-up resistor

Rpull

Internal pull-up

resistance to VDDIO

120

190

kΩ

I2C bus load capacitor

On SDI and SCK

400

5.4.2

I²C timings

For I²C timings, the following abbreviations are used:

•

“S&F mode” = standard and fast mode

•

“HS mode” = high speed mode

•

Cb = bus capacitance on SDA line

All other naming refers to I²C specification 2.1 (January 2000).

The I²C timing diagram is shown in

Figure 12. The corresponding values are given in Table 27

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