TMS320DM647 datasheet(21/166 Pages) TI

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TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

TYPE

INTERNAL

OPER

DESCRIPTION

PULLUP/

VOLT

PULLDOWN

PIRDY/HRDY

AB17

I/O/Z

IPD

3.3 V

PCI initiator ready [default] or host ready from DSP to host (O/Z)

PGNT/GP00

U13

I/O/Z

IPD

3.3 V

PCI bus grant (I) or GPIO[0]

PRST/GP01

U12

I/O/Z

IPD

3.3 V

PCI Reset (I) or GPIO[1]

PINTA/GP02

V12

I/O/Z

IPD

3.3 V

PCI Interrupt A (O/Z) or GPIO[2]

PREQ/GP03

AA12

I/O/Z

IPD

3.3 V

PCI bus request (O/Z) or GPIO[3]

PTRDY/GP05

AA17

I/O/Z

IPD

3.3 V

PCI target ready or GPIO[5]

PIDSEL/GP06

AA14

I/O/Z

IPD

3.3 V

PCI Initialization device select (I) or GPIO[6]

DDR2 MEMORY CONTROLLER

BBA0

C12

I/O/Z

1.8 V

DDR2 Memory Controller Bank Address Control

BBA1

B12

I/O/Z

1.8 V

BBA2

E11

I/O/Z

1.8 V

BCE

I/O/Z

1.8 V

DDR2 Memory Controller Memory Space Enable

BEA00

D15

I/O/Z

1.8 V

DDR2 Memory Controller External Address

BEA01

C15

I/O/Z

1.8 V

BEA02

F13

I/O/Z

1.8 V

BEA03

E14

I/O/Z

1.8 V

BEA04

D14

I/O/Z

1.8 V

BEA05

C14

I/O/Z

1.8 V

BEA06

F11

I/O/Z

1.8 V

BEA07

B14

I/O/Z

1.8 V

BEA08

F12

I/O/Z

1.8 V

BEA09

D13

I/O/Z

1.8 V

BEA10

A13

I/O/Z

1.8 V

BEA11

B13

I/O/Z

1.8 V

BEA12

E12

I/O/Z

1.8 V

BEA13

F10

I/O/Z

1.8 V

BECLKOUTN

A12

I/O/Z

1.8 V

DDR2 Memory Controller Output Clock (CLKIN2 frequency x 10)

BECLKOUTP

A11

I/O/Z

1.8 V

Negative DDR2 Memory Controller Output Clock (CLKIN2

frequency x 10)

BED00

I/O/Z

1.8 V

DDR2 Memory Controller External Data

BED01

I/O/Z

1.8 V

BED02

I/O/Z

1.8 V

BED03

I/O/Z

1.8 V

BED04

I/O/Z

1.8 V

BED05

I/O/Z

1.8 V

BED06

I/O/Z

1.8 V

BED07

I/O/Z

1.8 V

BED08

I/O/Z

1.8 V

BED09

I/O/Z

1.8 V

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