TMS320DM647 datasheet(20/166 Pages) TI

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TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

TYPE

INTERNAL

OPER

DESCRIPTION

PULLUP/

VOLT

PULLDOWN

AD00/HD00

AA22

I/O/Z

IPD

3.3 V

Host Port data [15:00] pin or PCI data-address bus [15:00]

[default]

AD01/HD01

AB22

I/O/Z

IPD

3.3 V

AD02/HD02

AC21

I/O/Z

IPD

3.3 V

AD03/HD03

AA23

I/O/Z

IPD

3.3 V

AD04/HD04

AC22

I/O/Z

IPD

3.3 V

AD05/HD05

AB21

I/O/Z

IPD

3.3 V

AD06/HD06

AA21

I/O/Z

IPD

3.3 V

AD07/HD07

Y21

I/O/Z

IPD

3.3 V

AD08/HD08

AB20

I/O/Z

IPD

3.3 V

AD09/HD09

AA20

I/O/Z

IPD

3.3 V

AD10/HD10

Y20

I/O/Z

IPD

3.3 V

AD11/HD11

Y19

I/O/Z

IPD

3.3 V

AD12/HD12

AB18

I/O/Z

IPD

3.3 V

AD13/HD13

AA19

I/O/Z

IPD

3.3 V

AD14/HD14

AC18

I/O/Z

IPD

3.3 V

AD15/HD15

AA18

I/O/Z

IPD

3.3 V

AD16/HD16

Y16

I/O/Z

IPD

3.3 V

Host Port data [31:16] pin or PCI data-address bus [31:16]

[default]

AD17/HD17

AB15

I/O/Z

IPD

3.3 V

AD18/HD18

AA15

I/O/Z

IPD

3.3 V

AD19/HD19

Y15

I/O/Z

IPD

3.3 V

AD20/HD20

W15

I/O/Z

IPD

3.3 V

AD21/HD21

V15

I/O/Z

IPD

3.3 V

AD22/HD22

AC14

I/O/Z

IPD

3.3 V

AD23/HD23

AB14

I/O/Z

IPD

3.3 V

AD24/HD24

W14

I/O/Z

IPD

3.3 V

AD25/HD25

V14

I/O/Z

IPD

3.3 V

AD26/HD26

AC13

I/O/Z

IPD

3.3 V

AD27/HD27

AB13

I/O/Z

IPD

3.3 V

AD28/HD28

AA13

I/O/Z

IPD

3.3 V

AD29/HD29

Y13

I/O/Z

IPD

3.3 V

AD30/HD30

W13

I/O/Z

IPD

3.3 V

AD31/HD31

V13

I/O/Z

IPD

3.3 V

PPAR/HAS

W19

I/O/Z

IPU

3.3 V

Host address strobe (I) or PCI parity [default]

PSTOP/HCNTL0

Y18

I/O/Z

IPD

3.3 V

Host Control selects between control, address, or data registers (I)

or PCI Stop [default]

PDEVSEL/HCNTL1

Y17

I/O/Z

IPD

3.3 V

Host Control selects between control, address, or data registers (I)

or PCI Device Select [default]

PPERR/HCS

W17

I/O/Z

IPU

3.3 V

Host chip select (I) or PCI parity error [default]

PSERR/ HDS1

W18

I/O/Z

IPU

3.3 V

Host data strobe 1 (I) or PCI system error [default]

PCBE0/GP04

AC20

I/O/Z

IPU

3.3 V

PCI command/byte enable 0 or GP[2] [default

PCBE1/HDS2

AC17

IPU

3.3 V

PCI command/byte enable 1 or host data strobe 2

PCBE2/HRW

W16

I/O/Z

IPU

3.3 V

PCI command/byte enable 2 or host read or write select (I)

PCBE3/GP07

Y14

I/O/Z

IPU

3.3 V

PCI command/byte enable 3 or GPIO[7]

PCLK/HHWIL

AC15

I/O/Z

IPU

3.3 V

PCI clock (I) [default] or host half-word select - first or second

half-word (not necessarily high or low order) [For HPI16 bus width

selection only] (I)

PFRAME/HINT

AA16

I/O/Z

IPD

3.3 V

PCI frame or host interrupt from DSP to host (O/Z)

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